Difference between revisions of "Yuzuki Avaota-A1"
Jump to navigation
Jump to search
| (31 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
[[File:Yuzuki_Avaota-A1-2.jpg|400px|thumb|right|The Yuzuki Avaota-A1]] | [[File:Yuzuki_Avaota-A1-2.jpg|400px|thumb|right|The Yuzuki Avaota-A1]] | ||
The '''Yuzuki''' is an ARM64 based Single Board Computer powered by Allwinner | The '''Yuzuki Avaota-A1''' is an ARM64 based Single Board Computer powered by Allwinner A527 Octa-Core ARM Cortex-A55 64-Bit CPU @2.0GHz, ARM Mali G56 GPU and RISC-V XuanTie E906 CPU@200MHz. It provides onboard eMMC, MicroSD Card slot, PCI-e, Pi-2 Bus, USB 3.0, and many other peripheral interfaces for makers to integrate with sensors and other devices. | ||
The releases are still in '''alpha''' state and are only fit for testing purposes. | The releases are still in '''alpha''' state and are only fit for testing purposes. | ||
* [https://forum.pine64.org/showthread.php?tid=18276 Armbian] | * [https://forum.pine64.org/showthread.php?tid=18276 Armbian] | ||
* | * [https://github.com/AvaotaSBC/openwrt/releases OpenWrt Github Release] | ||
== SoC and Memory Specification == | == SoC and Memory Specification == | ||
* Based on [https://www. | * Based on [https://www.allwinnertech.com/index.php?c=product&a=index&id=109 Allwinner A527] | ||
[[File: | [[File:Allwinner_A527-logo.png|right|200px]] | ||
[[File: | [[File:Allwinner-T527-A527-block-diagram.jpg |800px]] | ||
=== CPU Architecture === | === CPU Architecture === | ||
* [https:// | * [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55] at 2.0 GHz | ||
* AArch32 for full backwards compatibility with ARMv7 | |||
* | * ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation | ||
* | * Includes VFP hardware to support single and double-precision operations | ||
* 32KB L1 | * ARMv8 Cryptography Extensions | ||
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core | |||
* Integrated 64KB L2 instruction cache and 128KB L2 data cache per cluster | |||
* 1MB unified system L3 cache | |||
* Integrated | |||
* | |||
=== GPU Architecture === | === GPU Architecture === | ||
* [https://www. | * [https://www.arm.com/products/silicon-ip-multimedia/gpu/mali-g57 Mali-G57 Valhall GPU@850MHz] | ||
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop | |||
* | * 128KB L2 Cache configurations | ||
* | * Supports OpenGL ES 1.1, 2.0, and 3.2 | ||
* | * Supports Vulkan 1.1 | ||
* | * Supports OpenCL 1.1, 1.2, 2.0 Full Profile | ||
* | * Supports Renderscript | ||
* | * L2 Cache Configurable 64KB – 512KB | ||
* | ** 64KB-128KB for 1-Core | ||
** 128KB-256KB for 2-Core | |||
** 256KB for 3-Core | |||
** 1x256KB-2x256KB for 4-Core | |||
** 2x256KB-2x512KB for 5-Core and 6-Core configurations | |||
* Supports 3400 Mpix/s fill rate when at 850MHz clock frequency | |||
* Supports 243.2 GLOP/s when at 850MHz clock frequency for peak single precision (FP32) performance | |||
=== System Memory === | === System Memory === | ||
* LPDDR4 RAM Memory Variants: 2GB | * LPDDR4 RAM Memory Variants: 2GB and 4GB. | ||
== Board Features == | == Board Features == | ||
=== Video === | === Video === | ||
* Digital Video output up to 4K@ | * Digital Video output up to 4K@60Hz | ||
* H.264/AVC Base/Main/High/High10 profile @ level 5.1; up to 4K×2K @ 30fps | |||
* H.264/AVC Base/Main/High/High10 profile @ level 5.1; up to 4K×2K @ | |||
* H.265/HEVC Main/Main10 profile @ level 5.1 High-tier; up to 4K×2K @ 60fps | * H.265/HEVC Main/Main10 profile @ level 5.1 High-tier; up to 4K×2K @ 60fps | ||
| Line 59: | Line 62: | ||
=== Network === | === Network === | ||
* | * Dual 10/100/1000Mbps Ethernet | ||
* 2.4GHz/5Ghz MIMO WiFi 802.11 b/g/n/ac with Bluetooth 5.2 | * 2.4GHz/5Ghz MIMO WiFi 802.11 b/g/n/ac with Bluetooth 5.2 | ||
| Line 65: | Line 68: | ||
* on-board 128Mbit (16MByte) XSPI NOR flash memory - bootable | * on-board 128Mbit (16MByte) XSPI NOR flash memory - bootable | ||
* microSD - bootable, supports SDHC and SDXC and storage up to 256GB | * microSD - bootable, supports SDHC and SDXC and storage up to 256GB | ||
* eMMC - bootable | * eMMC - bootable on-board 16GB or 32GB | ||
=== Expansion Ports === | === Expansion Ports === | ||
* 2×20 pins "Pi2" GPIO Header | * 2×20 pins "Pi2" GPIO Header | ||
[[File:Avaota-A1_40_pin_connector layout.jpg |1200px]] | |||
* 4 lane MiPi DSI port for LCD panel | * 4 lane MiPi DSI port for LCD panel | ||
* 4 lane MiPi CSI port for camera module | * 4 lane MiPi CSI port for camera module | ||
* 1× USB3.0 OTG port | |||
* 1× USB2.0 Host port | |||
* 1× USB2.0 OTG port | |||
* 1× CAN port | |||
== Board Information, Schematics and Certifications == | == Board Information, Schematics and Certifications == | ||
[[File:AvaotaA1 Dimention.jpg|800px]] | |||
Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector | Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector | ||
Schematic: | Schematic: | ||
* [https:// | * [https://github.com/AvaotaSBC/Avaota-A1/blob/master/hardware/v1.7/01_SCH/SCH_Avaota%20Pi%20A_2_2024-08-30.pdf Yuzuki Avaota-A1 Schematic v1.7] | ||
Board map of connectors with schematic v1.1 identifiers: | Board map of connectors with schematic v1.1 identifiers: | ||
[[File: | [[File:Avaota-A1_SBC_layout.jpg|800px]] | ||
Certifications: | Certifications: | ||
| Line 96: | Line 104: | ||
== Datasheets for Components and Peripherals == | == Datasheets for Components and Peripherals == | ||
Allwinner A527 SoC information: | |||
* [https:// | * [https://gitlab.com/tina5.0_aiot/product/docs/-/blob/product-aiot-stable/A527/Hardware硬件类文档/芯片手册/A527_User_Manual_V0.94.pdf Allwinner A527 SoC Product Brief] | ||
* [https:// | * [https://gitlab.com/tina5.0_aiot/product/docs/-/blob/product-aiot-stable/A527/Hardware硬件类文档/芯片手册/A527_Datasheet_V0.93.pdf Allwinner A527 SoC Datasheet] | ||
* [https:// | * [https://gitlab.com/tina5.0_aiot/product/docs/-/blob/product-aiot-stable/A527/Hardware硬件类文档/芯片手册/A527_User_Manual_V0.94.pdf Allwinner SoC User Reference Manual] | ||
X-Power PMU information: | X-Power PMU information: | ||
* [https:// | * [https://gitlab.com/tina5.0_aiot/product/docs/-/blob/product-aiot-stable/A527/Hardware硬件类文档/芯片手册/A527_User_Manual_V0.94.pdf Allwinner AXP717 PMU Product Brief] | ||
* [https://gitlab.com/tina5.0_aiot/product/docs/-/blob/product-aiot-stable/A527/Hardware硬件类文档/芯片手册/A527_User_Manual_V0.94.pdf Allwinner AXP717 PMU Datasheet] | |||
LPDDR4 (200 Balls) SDRAM: | LPDDR4 (200 Balls) SDRAM: | ||
* [https://files.pine64.org/doc/datasheet/ | * [https://files.pine64.org/doc/datasheet/yuzuki_avaota-a1/RS512M32LO4D1BDS-53BT.pdf RaysonLPDDR4 Datasheet] | ||
eMMC information: | eMMC information: | ||
* [https://files.pine64.org/doc/datasheet/yuzuki_avaota-a1/EMMC04G-MT32.pdf Kingston eMMC Datasheet] | |||
* [https://files.pine64.org/doc/datasheet/ | |||
Ethernet related info: | Ethernet related info: | ||
* | * [https://files.pine64.org/doc/datasheet/rock64/RTL8211F-CG-Realtek.pdf Realtek RTL8211F 10/100/1000M Ethernet Transceiver Datasheet] | ||
WiFi/BT module info: | WiFi/BT module info: | ||
* [https://files.pine64.org/doc/datasheet/ | * [https://files.pine64.org/doc/datasheet/yuzuki_avaota-a1/SKI.WB800D80S.1_D40%20datasheet_V1.2_20231018.pdf AICSemi 8800D40 module 11AC Dual Band 2T2R WiFi + Bluetooth5.2 Datasheet] | ||
* [https://files.pine64.org/doc/datasheet/quartz64/AIC8800DC%20Datasheet%20v1.0.pdf AICSemi AIC8800DC 11AX Wi-Fi + Bluetooth5.2 Datasheet] | |||
* | |||
[[Category:Yuzuki Avaota-A1]] | [[Category:Yuzuki Avaota-A1]] | ||
Latest revision as of 22:39, 14 June 2026
The Yuzuki Avaota-A1 is an ARM64 based Single Board Computer powered by Allwinner A527 Octa-Core ARM Cortex-A55 64-Bit CPU @2.0GHz, ARM Mali G56 GPU and RISC-V XuanTie E906 CPU@200MHz. It provides onboard eMMC, MicroSD Card slot, PCI-e, Pi-2 Bus, USB 3.0, and many other peripheral interfaces for makers to integrate with sensors and other devices.
The releases are still in alpha state and are only fit for testing purposes.
SoC and Memory Specification
- Based on Allwinner A527
CPU Architecture
- Quad-core ARM Cortex-A55 at 2.0 GHz
- AArch32 for full backwards compatibility with ARMv7
- ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
- Includes VFP hardware to support single and double-precision operations
- ARMv8 Cryptography Extensions
- Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
- Integrated 64KB L2 instruction cache and 128KB L2 data cache per cluster
- 1MB unified system L3 cache
GPU Architecture
- Mali-G57 Valhall GPU@850MHz
- 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
- 128KB L2 Cache configurations
- Supports OpenGL ES 1.1, 2.0, and 3.2
- Supports Vulkan 1.1
- Supports OpenCL 1.1, 1.2, 2.0 Full Profile
- Supports Renderscript
- L2 Cache Configurable 64KB – 512KB
- 64KB-128KB for 1-Core
- 128KB-256KB for 2-Core
- 256KB for 3-Core
- 1x256KB-2x256KB for 4-Core
- 2x256KB-2x512KB for 5-Core and 6-Core configurations
- Supports 3400 Mpix/s fill rate when at 850MHz clock frequency
- Supports 243.2 GLOP/s when at 850MHz clock frequency for peak single precision (FP32) performance
System Memory
- LPDDR4 RAM Memory Variants: 2GB and 4GB.
Board Features
Video
- Digital Video output up to 4K@60Hz
- H.264/AVC Base/Main/High/High10 profile @ level 5.1; up to 4K×2K @ 30fps
- H.265/HEVC Main/Main10 profile @ level 5.1 High-tier; up to 4K×2K @ 60fps
Audio
- 3.5mm audio Jack
Network
- Dual 10/100/1000Mbps Ethernet
- 2.4GHz/5Ghz MIMO WiFi 802.11 b/g/n/ac with Bluetooth 5.2
Storage
- on-board 128Mbit (16MByte) XSPI NOR flash memory - bootable
- microSD - bootable, supports SDHC and SDXC and storage up to 256GB
- eMMC - bootable on-board 16GB or 32GB
Expansion Ports
- 2×20 pins "Pi2" GPIO Header
- 4 lane MiPi DSI port for LCD panel
- 4 lane MiPi CSI port for camera module
- 1× USB3.0 OTG port
- 1× USB2.0 Host port
- 1× USB2.0 OTG port
- 1× CAN port
Board Information, Schematics and Certifications
Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector
Schematic:
Board map of connectors with schematic v1.1 identifiers:
Certifications:
- Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary. However, PINE64 still submits the SBC for FCC, CE, and ROHS certifications and obtain the certificates to prove that the SBC board can pass the testing. Please note, a final commercial product needs to perform its own testing and obtain its own certificate.
- Not yet available
Datasheets for Components and Peripherals
Allwinner A527 SoC information:
X-Power PMU information:
LPDDR4 (200 Balls) SDRAM:
eMMC information:
Ethernet related info:
WiFi/BT module info:





