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===P.4 LPDDR3 FPGA178===
 
<div style="margin-left:20px">'''''Note:''''' The title of this schematic page should be changed from "LPDDR3 FPGA178" to "LPDDR3 FBGA178", because the RAM chip is a 178-pin fine pitch ball grid array (FBGA), not a field-programmable gate array (FPGA).</div>
* DU1:<br>Artmem [http://files.pine64.org/doc/datasheet/pinephone/ATL3A1632H12A_mobile_lpddr3_11x11.5_v1.0_1600.pdf ATL3A1632H12A] 2GB 800MHz LPDDR3-1600 SDRAM, FBGA-178 11.0x11.5x0.93 mm<br>'''''Note:''''' RAM will be clocked slower at 667MHz, because the Allwinner A64 only supports up to 3GB LPDDR3-1333.<br>
 
'''''Note:''''' The title of this schematic page should be changed from "LPDDR3 FPGA178" to "LPDDR3 FBGA178", because the RAM chip is a 178-pin fine pitch ball grid array (FBGA), not a field-programmable gate array (FPGA).
===P.5 CPU===
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