The following is the documentation draft for a proposed new PINE64 storage product, PineFlash. As such, PineFlash is proposed by the community and, as of April 2021, is neither endorsed nor acknowledged by PINE64 as a possible new official PINE64 product. This content is the result of initial discussions about this storage device, documented in this forum thread.
Please, consider joining us for discussion in IRC.
The aim of this project is to create an open-hardware USB flash drive, hence the name PineFlash, which can act as the basis of future projects in the area of open storage. An open-hardware flash device with open-source firmware would allow the community to address storage safety and information security. Additionally, issues such as speed, functionality and compatibility could also be addressed.
|Read speed||12 Mbit/s (Full-Speed USB 1.x)||480 Mbit/s (High-Speed USB 2.0)|
|Write speed||12 Mbit/s (Full-Speed USB 1.x)||480 Mbit/s (High-Speed USB 2.0)|
This is intended to document the project direction towards a manufacturing-viable device.
The initial idea is for the storage device to be in form of a "hat" for one of the BL602 devices manufactured and sold by PINE64, such as the Nutcracker board.
TO-DO: Plan out hardware steps.
- USB 1.x speed mass storage device, no real storage. Get the controller presenting itself as a mass storage device. Data read and written will just be placeholder data to prove that the USB communication is working correctly.
- Single flash chip selected for storage - quad-SPI. Prove out that we can select a single flash chip, store data to it and read it back. This proves our understanding of the quad-SPI interface and implement some basic interface for communicating with a single flash chip.
- Multiple flash chips selected for storage - quad-SPI. Prove that we can communicate with multiple flash chips via quad-SPI.
This is the documentation of the initial prototype design.
The initial prototype is intended to be a "hat" for the community-driven Nutcracker project, based on the BL602 SoC. The CPU core is RISC-V (as the final controller is planned to be) and the SoC supports a quad-SPI flash interface.
TO-DO: The proposed schematic for the device.
TO-DO: The bill of materials used in the schematic.
TO-DO: The PCB design for the device.
The work on the BL602 is to be on-top of the documented work by Lupyuen.
TO-DO: Document the prototype's software stack.
- TinyUSB - An open source software stack for slave USB devices
TO-DO: Figure out exactly how the prototype will be tested to ensure robustness and performance.
This is a list of suggested features, collated and attributed (where possible). This list is not meant to encapsulate every possible idea or suggestion, just a series of plausible ones that can be considered within the scope of this project.
- Type-A & Type-C USB interfaces (barray)
- RAID (barray)
- Dynamically adjusted wear leveling pool (Arwen)
- Keep 2 copies of the wear leveling & indirect table, with checksum, to avoid corruption (Arwen)
- USB Attached SCSI (UASP) (Arwen)
- SMART (probably requires UASP first) (Arwen)
- Ability to define and enforce write barriers (dsimic)
- Fingerprint scanner (Julius_GU)
- Lit Pine logo on casing (Julius_GU)