Difference between revisions of "STAR64"

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* Based on [https://www.starfivetech.com/en/site/soc StarFive JH7110]
* Based on [https://www.starfivetech.com/en/site/soc StarFive JH7110]
[[File:StarFive.jpg|right]]
[[File:StarFive.jpg|right]]
[[File:JH7110_Block_Diagram.jpg|400px|thumb]]
=== CPU Architecture ===
* [https://www.sifive.com/cores/u74 Quad-core U74 up to 1.5GHz CPU]
* Fully compliant with the RISC-V ISA specification
* 64-bit RISC-V Application Core
* 32KB L1 I-cache with ECC
* 32KB L1 D-cache with ECC
* 8 Region Physical Memory Protection
* Virtual Memory support with up to 47 Physical Address bits
* Integrated up to 2MB L2 Cache with ECC
* includes RV64IMAC S7 monitor core, 16 KB L1 I-Cache with ECC, 8 KB DTIM with ECC
* 32-bit RISC-V CPU core (E24) for real time control, support RV32IMFC RISC-V ISA

Revision as of 20:50, 24 September 2022

The STAR64

The Star64 is a RISC-V based Single Board Computer powered by StarFive JH7110 Quad-Core SiFive U74 64-Bit CPU, Imagination Technology BX-4-32 GPU and supports up to 8GB 1866MHz LPDDR4 memory. It provides an eMMC module socket, MicroSD Card slot, PCI-e, Pi-2 Bus, USB 3.0, and many other peripheral interfaces for makers to integrate with sensors and other devices.


Software releases

Quick Links to the Source of OS Images Build

OS images are still in alpha build which are only fit for board bring up and testing purposes.













SoC and Memory Specification

StarFive.jpg
JH7110 Block Diagram.jpg


CPU Architecture

  • Quad-core U74 up to 1.5GHz CPU
  • Fully compliant with the RISC-V ISA specification
  • 64-bit RISC-V Application Core
  • 32KB L1 I-cache with ECC
  • 32KB L1 D-cache with ECC
  • 8 Region Physical Memory Protection
  • Virtual Memory support with up to 47 Physical Address bits
  • Integrated up to 2MB L2 Cache with ECC
  • includes RV64IMAC S7 monitor core, 16 KB L1 I-Cache with ECC, 8 KB DTIM with ECC
  • 32-bit RISC-V CPU core (E24) for real time control, support RV32IMFC RISC-V ISA