Difference between revisions of "ROCK64"

From PINE64
Jump to navigation Jump to search
m (→‎Upstreaming Status: Remove leftover extra pipe)
m (→‎SoC and Memory Specification: Grammar edit, minor additions)
Line 135: Line 135:
  
 
=== CPU Architecture ===
 
=== CPU Architecture ===
* [https://www.arm.com/products/processors/cortex-a/cortex-a53-processor.php Quad-core Cortex-A53 up to 1.5GHz CPU]
+
* [https://www.arm.com/products/processors/cortex-a/cortex-a53-processor.php Quad-core Cortex-A53 up to 1.5GHz CPU] running at 1296 MHz
 
* Full implementation of the ARM architecture v8-A instruction set
 
* Full implementation of the ARM architecture v8-A instruction set
 
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
 
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
Line 141: Line 141:
 
* In-order pipeline with symmetric dual-issue of most instructions
 
* In-order pipeline with symmetric dual-issue of most instructions
 
* Unified system L2 cache
 
* Unified system L2 cache
* Include VFP v3 hardware to support single and double-precision operations
+
* Includes VFP v3 hardware to support single and double-precision operations
* Integrated 32KB L1 instruction cache, 32KB L1 data cache with 4-way set associative
+
* Integrated 32KB L1 instruction cache, 32KB 4-way set associative L1 data cache
 
* TrustZone technology support
 
* TrustZone technology support
 
* Full CoreSight debug solution
 
* Full CoreSight debug solution
* One separate power domains for CPU core system to support internal power switch and externally turn on/off based on different application scenario
+
* One separate power domain for CPU core system to support internal power switch, and to externally turn on/off based on different application scenario
 
* PD_A53: Cortex-A53 + Neon + FPU + L1 I/D Cache of core 2/3
 
* PD_A53: Cortex-A53 + Neon + FPU + L1 I/D Cache of core 2/3
 
* One isolated voltage domain to support DVFS
 
* One isolated voltage domain to support DVFS

Revision as of 06:49, 14 May 2021

ROCK64

ROCK64 is a credit-card size 4K60P HDR Media Board Computer powered by Rockchip RK3328 Quad-Core ARM Cortex A53 64-Bit Processor and supports up to 4GB 1866MHz LPDDR3 memory. It provides an eMMC module socket, MicroSD Card slot, Pi-2 Bus, Pi-P5+ Bus, USB 3.0, and many other peripheral interfaces for makers to integrate with sensors and other devices. Many different Operating Systems (OS) are freely available from the open source community, such as Android 7.1, Debian, and Yocto.

ROCK64 sideimg.jpg

ROCK64 Software Images

Under ROCK64 Software Release you will find a complete list of currently supported Operating System images that work with the ROCK64 as well as other related software.

The list includes OS images and descriptions of:


Quick Links to the Source of OS Images Build

Some OS images are still in beta or nightly build which are only fit for testing purposes. These should usually be avoided for normal usage, since they are used at your own risk

State of software support for the hardware

Requirement GNU/Linux Android/Linux Kodi/Linux
2160p 30Hz 8bit h264/h265/vp8 partial? 1 yes yes
UI using GPU no yes yes
Youtube no yes no
vp9 / mpeg4 / mpeg2 / 10bit HDR / YCbCr no yes? yes

Upstreaming Status

Function Status Component Notes
Video Output Linux Mainline rockchipdrm With mpv, you'll need to specify something like mpv --gpu-context=drm --drm-connector=1.HDMI-A-1 to get it to play back on a VT
3D Acceleration Linux Mainline Upstream Mesa lima Very recent version recommended for the best experience
Video Decode Linux Mainline Not in ffmpeg hantro_vpu, using v4l2m2m Moved out of staging in 5.13, ffmpeg patch set seemingly abandoned as no response was made to a patch review in several months. Git branch with commits
Audio Linux Mainline snd_soc_rockchip_*

SoC and Memory Specification

  • Based on Rockchip RK3328
Rockchip RK3328.png

CPU Architecture

  • Quad-core Cortex-A53 up to 1.5GHz CPU running at 1296 MHz
  • Full implementation of the ARM architecture v8-A instruction set
  • ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
  • ARMv8 Cryptography Extensions
  • In-order pipeline with symmetric dual-issue of most instructions
  • Unified system L2 cache
  • Includes VFP v3 hardware to support single and double-precision operations
  • Integrated 32KB L1 instruction cache, 32KB 4-way set associative L1 data cache
  • TrustZone technology support
  • Full CoreSight debug solution
  • One separate power domain for CPU core system to support internal power switch, and to externally turn on/off based on different application scenario
  • PD_A53: Cortex-A53 + Neon + FPU + L1 I/D Cache of core 2/3
  • One isolated voltage domain to support DVFS

GPU Architecture

System Memory

  • LPDDR3 RAM Memory Variants: 1GB, 2GB and 4GB.

Board Features

Video

  • Digital Video output up to 4K@60Hz
  • 4K HDR @ 60fps
  • H.264/AVC Base/Main/High/High10 profile @ level 5.1; up to 4Kx2K @ 60fps
  • H.265/HEVC Main/Main10 profile @ level 5.1 High-tier; up to 4Kx2K @ 60fps
  • VP9, up to 4Kx2K @ 60fps
  • MPEG-1, ISO/IEC 11172-2, up to 1080P @ 60fps
  • MPEG-2, ISO/IEC 13818-2, SP@ML, MP@HL, up to 1080P @ 60fps
  • MPEG-4, ISO/IEC 14496-2, SP@L0-3, ASP@L0-5, up to 1080P @ 60fps
  • VC-1, SP@ML, MP@HL, AP@L0-3, up to 1080P @ 60fps
  • MVC is supported based on H.264 or H.265, up to 1080P @ 60fps

Audio

  • 3.5mm A/V Jack (Composite Video Output and RCA Stereo support using conversion cable)

Network

  • 10/100/1000Mbps Ethernet
  • WiFi 802.11 b/g/n with Bluetooth 4.0 (optional USB dongle)

Storage

  • microSD - bootable, support SDHC and SDXC, storage up to 256GB
  • eMMC - bootable (optional eMMC Module)
  • 128Mbit (16MB) on-board SPI flash memory (empty by default) - bootable?
  • 1 USB3.0 Dedicated Host port
  • 2 USB2.0 Dedicated Host port (top one is USB-OTG)

Expansion Ports

  • 2x20 pins "Pi2" GPIO Header
  • 2x11 pins "Pi P5+" GPIO Header (with 2nd 10/100Mbps Ethernet pins)

ROCK64 Board Information, Schematics and Certifications

https://files.pine64.org/doc/rock64/R64V3%20RTC%20Batt%20connector.png ROCK64 Rev3 SBC RTC Battery Connector polarity

Datasheets for Components and Peripherals

Other Resources