Difference between revisions of "Quartz64"

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* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core Cortex-A55@1.8GHz]
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core Cortex-A55@1.8GHz]


* A power-efficient ARM 64-Bit Armv8-A architecture
* Quad-core ARM Cortex-A55 CPU
* AArch32 for full backward compatibility with Armv7
* AArch32 for full backward compatibility with Armv7
* Support NEON Advanced SIMD (Single Instruction Multiple Data) instruction for acceleration of media and signal processing function
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Support Large Physical Address Extensions(LPAE)
* Include VFP hardware to support single and double-precision operations
* VFPv4 Floating Point Unit
* ARMv8 Cryptography Extensions
* 32KB L1 Instruction cache and 32KB L1 Data cache
* Integrated 32KB L1 instruction cache, 32KB L1 data cache
* AArch64 for 64-bit support and new architectural features
* 512KB unified system L3 cache
* TrustZone security technology
* TrustZone technology support
* Neon Advanced SIMD
* DSP and SIMD extensions
* VFPv4 Floating point
* Hardware virtualization support
* 128KB L2 cache




=== Graphic Process Unit GPU Capability ===
=== Graphic Process Unit GPU Capability ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@850MHz]
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop.
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop  
* 128KB L2 Cache configurations.   
* 128KB L2 Cache configurations
* Support OpenGL ES 1.1, 2.0, and 3.2
* Support Vulkan 1.0 and 1.1
* Support OpenCL 2.0 Full Profile
* Support 1600Mpix/s fill rate when 800MHz clock frequency
* Support 38.4GLOPs when 800MHz clock frequency    
 
 
=== Neural Process Unit NPU Capability ===
* Neural network acceleration engine with processing performance up to 0.8 TOPS
* Support integer 8, integer 16 convolution operation
* Support deeplearning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet
 


=== System Memory ===
=== System Memory ===
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=== Expansion Ports ===
=== Expansion Ports ===
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1080P
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* CSI - CMOS Camera Interface up to 5 mega pixel
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* TP - Touch Panel Port, SPI with interrupt
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header
* 2x20 pins "Pi2" GPIO Header on model B, 2x5 pins GPO header on
* PCIe 2x open ended slot
* PCIe 2x open ended slot on model A, m.2 slot on model B


== SOEdge Module and Baseboard Information, Schematics, and Certifications ==
== Quartz64 board Information, Schematics, and Certifications ==
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5OD/2.1ID Barrel DC Jack connector
* Input Power: DC 12V @ 3A 5.5OD/2.1ID Barrel DC Jack connector


* SOEdge Module Schematic:
** [https://files.pine64.org/doc/SOEdge/SOEdge-Schematic-v2.0-190919.pdf SOEdge Module ver 2.0 20190919 Schematic]
** [https://files.pine64.org/doc/SOEdge/SoEdge-PCB-placement-v2.0-topplace.pdf SOEdge Module ver 2.0 20190919 PCB Component Placement Top PDF file]
** [https://files.pine64.org/doc/SOEdge/SoEdge-PCB-placement-v2.0-bottomplace.pdf SOEdge Module ver 2.0 20190919 PCB Component Placement Bottom PDF file]
** [https://files.pine64.org/doc/SOEdge/SoEdge-PCB-placement-v2.0-topplace.dxf SOEdge Module ver 2.0 20190919 PCB Component Placement Top Drawing file]
** [https://files.pine64.org/doc/SOEdge/SoEdge-PCB-placement-v2.0-bottomplace.dxf SOEdge Module ver 2.0 20190919 PCB Component Placement Bottom Drawing file]
** [https://files.pine64.org/doc/SOEdge/SOEdge%20Pin%20Assignments%20ver%201.00.xlsx SOEdge Module Pin Assignment ver 1.0 in Excel format(includes comparison chart to SOPine)]
** [https://files.pine64.org/doc/SOEdge/SOEdge%20Pin%20Assignments%20ver%201.00.ods SOEdge Module Pin Assignment ver 1.0 in Open Document format(includes comparison chart to SOPine)]
* SOEdge Model "A" Baseboard Schematic and PCB Board Resource:
* SOEdge Model "A" Baseboard Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/SOEdge/SoEdge_Baseboard%20Schematic%20Model%20A-20200513.pdf SOEdge Model "A" Baseboard Schematic 20200513 PDF file]
** [https://files.pine64.org/doc/SOEdge/SoEdge_Baseboard%20Schematic%20Model%20A-20200513.pdf SOEdge Model "A" Baseboard Schematic 20200513 PDF file]
** [https://files.pine64.org/doc/SOEdge/SoEdge_Baseboard_PCB_layout_Model_A2020-05-31.pdf SOEdge Model "A" Baseboard PCB Layout PDF file]
** [https://files.pine64.org/doc/SOEdge/SoEdge_Baseboard_PCB_layout_Model_A2020-05-31.pdf SOEdge Model "A" Baseboard PCB Layout PDF file]
* SOEdge Neural AI Stick Schematic:
* Wifi/BT module Schematic for model A
** [https://files.pine64.org/doc/SOEdge/SOEdge%20Neural%20AI%20Stick%20Schematic_V10.pdf SOEdge Neural AI Stick PDF file]
* [https://files.pine64.org/doc/rockpro64/rockpro64_wifi_ap6359SA.pdf ROCKPro64 AP6359SA Wifi/BT Schematic]
* SOEdge/SOPine/PINE A64 Wifi/BT module Schematic
* Certification:
** [https://files.pine64.org/doc/Pine%20A64%20Schematic/A64-DB-WIFI-BT-REV%20B.pdf PINE A64 Wifi/BT Module Schematic]
* SOEdge module together with model "A" baseboard Certification:
** Disclaimer: Please note that SOEdge module is not a "final" product and in general certification is not necessary. However, SOEdge module still submits the mpdel A baseboard for FCC, CE, and ROHS certifications and obtain the certificates to prove that can pass the testing. Please note, a final commercial product needs to perform its own testing and obtain its own certificate.
** Not yet available
** Not yet available


Revision as of 01:47, 10 February 2021

The SOEdge is a 3TOPS compute module that can be paired with the SOPine base board or USB 3.0 and PCIe adapters for development. It can connect to a SBC, such as the ROCKPro64 or a regular PC.

Software and OS Image Downloads

SOEdge Software Release

  • TBD

SoC and Memory Specification

RK1808 icon.png

CPU Architecture

  • Quad-core ARM Cortex-A55 CPU
  • AArch32 for full backward compatibility with Armv7
  • ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
  • Include VFP hardware to support single and double-precision operations
  • ARMv8 Cryptography Extensions
  • Integrated 32KB L1 instruction cache, 32KB L1 data cache
  • 512KB unified system L3 cache
  • TrustZone technology support


Graphic Process Unit GPU Capability

  • Mali-G52 2EE Bifrost GPU@800MHz
  • 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
  • 128KB L2 Cache configurations
  • Support OpenGL ES 1.1, 2.0, and 3.2
  • Support Vulkan 1.0 and 1.1
  • Support OpenCL 2.0 Full Profile
  • Support 1600Mpix/s fill rate when 800MHz clock frequency
  • Support 38.4GLOPs when 800MHz clock frequency


Neural Process Unit NPU Capability

  • Neural network acceleration engine with processing performance up to 0.8 TOPS
  • Support integer 8, integer 16 convolution operation
  • Support deeplearning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet


System Memory

  • RAM Memory Variants: 2GB - 8GB LPDDR4.
  • Storage Memory: SPI Flash and optional eMMC module from 16GB up to 128GB


Network

  • 10/100/1000Mbps Ethernet
  • WiFi 802.11 b/g/n;ac with Bluetooth 5.0 (optional on model A)

Storage

  • microSD - bootable, support SDHC and SDXC, storage up to 256GB
  • USB - 2 USB 2.0 Host port, 1 USB 3.0 Host port
  • native SATA 2.0 Port (only on model A, share with USB 3.0 host port)

Expansion Ports

  • eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
  • DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
  • CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
  • TP - Touch Panel Port, SPI with interrupt on model A
  • RTC - Real Time Clock Battery Connector
  • VBAT - Lithium Battery Connector with temperature sensor input on model A
  • Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
  • 2x20 pins "Pi2" GPIO Header on model B, 2x5 pins GPO header on
  • PCIe 2x open ended slot on model A, m.2 slot on model B

Quartz64 board Information, Schematics, and Certifications

  • Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
  • Input Power: DC 12V @ 3A 5.5OD/2.1ID Barrel DC Jack connector

Datasheets for Components and Peripherals

SOEdge/SOPine Cluster Board Resource

Other Resources

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