Difference between revisions of "Quartz64"

From PINE64
Jump to navigation Jump to search
(Created page with "The SOEdge is a 3TOPS compute module that can be paired with the SOPine base board or USB 3.0 and PCIe adapters for development. It can connect to a SBC, such as the ROCKPro64...")
 
m (Minor corrections)
(24 intermediate revisions by 4 users not shown)
Line 1: Line 1:
The SOEdge is a 3TOPS compute module that can be paired with the SOPine base board or USB 3.0 and PCIe adapters for development. It can connect to a SBC, such as the ROCKPro64 or a regular PC.  
The Quartz64 is the most recent Single Board Computer offering from Pine64, scheduled for release in 2021. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.
 
Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.
 
The Quartz64 is equipped with 2GB, 4GB or 8GB LPDDR4 system memory, and 128Mb SPI boot Flash. There is also an optional eMMC module (up to 128GB) and microSD slot for booting. The board is equipped with 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, eink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.


== Software and OS Image Downloads ==
== Software and OS Image Downloads ==
=== SOEdge Software Release ===


* TBD
* TBD


== SoC and Memory Specification ==
== SoC and Memory Specification ==
* Based on [https://www.rock-chips.com/a/en/products/RK18_Series/2019/0529/989.html Rockchip RK1808]
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK1808_icon.png|right]]
[[File:RK3566_icon.png|right]]


=== CPU Architecture ===
=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a35 Dual-core ARM Cortex-A35 Processor@1600-2000Mhz]
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core Cortex-A55@1.8GHz]
* A power-efficient ARM 64-Bit Armv8-A architecture
 
* Quad-core ARM Cortex-A55 CPU
* AArch32 for full backward compatibility with Armv7
* AArch32 for full backward compatibility with Armv7
* Support NEON Advanced SIMD (Single Instruction Multiple Data) instruction for acceleration of media and signal processing function
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Support Large Physical Address Extensions(LPAE)
* Include VFP hardware to support single and double-precision operations
* VFPv4 Floating Point Unit
* ARMv8 Cryptography Extensions
* 32KB L1 Instruction cache and 32KB L1 Data cache
* Integrated 32KB L1 instruction cache, 32KB L1 data cache
* AArch64 for 64-bit support and new architectural features
* 512KB unified system L3 cache
* TrustZone security technology
* TrustZone technology support
* Neon Advanced SIMD
* DSP and SIMD extensions
* VFPv4 Floating point
* Hardware virtualization support
* 128KB L2 cache


=== Graphic Process Unit GPU Capability ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Support OpenGL ES 1.1, 2.0, and 3.2
* Support Vulkan 1.0 and 1.1
* Support OpenCL 2.0 Full Profile
* Support 1600Mpix/s fill rate when 800MHz clock frequency
* Support 38.4GLOPs when 800MHz clock frequency 


=== Neural Process Unit NPU Capability ===
=== Neural Process Unit NPU Capability ===
* [https://www.verisilicon.com/en/IPPortfolio/VivanteNPUIP NPU IP from Verisilicon Vivante]
* Neural network acceleration engine with processing performance up to 0.8 TOPS
* Support max 1920 Int8 MAC operation per cycle
* Support integer 8, integer 16 convolution operation
* Support max192 Int16 MAC operation per cycle
* Support deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet
* Support max 64 FP16 MAC operation per cycle
* 512KB internal buffer
* One isolated voltage domain to support DVFS
* [https://github.com/VeriSilicon/acuity-models Acuity models Github]
 
[[File:Vivante_Acuity_SDK.jpg]]


=== System Memory ===
=== System Memory ===
* RAM Memory Variants: 2GB DDR4.
* RAM Memory Variants: 2GB - 8GB LPDDR4.
* Storage Memory: SPI Flash and optional eMMC module from 16GB up to 128GB
* SPI Flash: 128Mbit / 16MByte
 
== SOEdge Baseboard Features ==


=== Network ===
=== Network ===
* 10/100/1000Mbps Etherne
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n with Bluetooth 4.0 (optional)
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, build in on model B)


=== Storage ===
=== Storage ===
* microSD - bootable, support SDHC and SDXC, storage up to 256GB
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB - 2 USB2.0 Host port
* USB - 2 ports on model B, 3 ports on model A USB 2.0 Host port, 1 USB 3.0 Host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 16GB up to 128GB


=== Expansion Ports ===
=== Expansion Ports ===
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1080P
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* CSI - CMOS Camera Interface up to 5 mega pixel
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* TP - Touch Panel Port, SPI with interrupt
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe 2x open ended slot
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints


== SOEdge Module and Baseboard Information, Schematics, and Certifications ==
== Quartz64 board Information, Schematics, and Certifications ==
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5OD/2.1ID Barrel DC Jack connector
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector
 
* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v1.0_20201124.pdf Quartz64 Model "A" SBC Schematic ver 1.0 20201124 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V1.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]


* SOEdge Module Schematic:
* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
** [https://files.pine64.org/doc/SOEdge/SOEdge-Schematic-v2.0-190919.pdf SOEdge Module ver 2.0 20190919 Schematic]
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID Barrel DC Jack connector
** [https://files.pine64.org/doc/SOEdge/SoEdge-PCB-placement-v2.0-topplace.pdf SOEdge Module ver 2.0 20190919 PCB Component Placement Top PDF file]
 
** [https://files.pine64.org/doc/SOEdge/SoEdge-PCB-placement-v2.0-bottomplace.pdf SOEdge Module ver 2.0 20190919 PCB Component Placement Bottom PDF file]
* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/SOEdge/SoEdge-PCB-placement-v2.0-topplace.dxf SOEdge Module ver 2.0 20190919 PCB Component Placement Top Drawing file]
** Quartz64 Model "B" SBC Schematic not yet available
** [https://files.pine64.org/doc/SOEdge/SoEdge-PCB-placement-v2.0-bottomplace.dxf SOEdge Module ver 2.0 20190919 PCB Component Placement Bottom Drawing file]
** [https://files.pine64.org/doc/quartz64/Quartz64%20model-B%20PCB%20placement.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]
** [https://files.pine64.org/doc/SOEdge/SOEdge%20Pin%20Assignments%20ver%201.00.xlsx SOEdge Module Pin Assignment ver 1.0 in Excel format(includes comparison chart to SOPine)]
 
** [https://files.pine64.org/doc/SOEdge/SOEdge%20Pin%20Assignments%20ver%201.00.ods SOEdge Module Pin Assignment ver 1.0 in Open Document format(includes comparison chart to SOPine)]
* Certification:
* SOEdge Model "A" Baseboard Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/SOEdge/SoEdge_Baseboard%20Schematic%20Model%20A-20200513.pdf SOEdge Model "A" Baseboard Schematic 20200513 PDF file]
** [https://files.pine64.org/doc/SOEdge/SoEdge_Baseboard_PCB_layout_Model_A2020-05-31.pdf SOEdge Model "A" Baseboard PCB Layout PDF file]
* SOEdge Neural AI Stick Schematic:
** [https://files.pine64.org/doc/SOEdge/SOEdge%20Neural%20AI%20Stick%20Schematic_V10.pdf SOEdge Neural AI Stick PDF file]
* SOEdge/SOPine/PINE A64 Wifi/BT module Schematic
** [https://files.pine64.org/doc/Pine%20A64%20Schematic/A64-DB-WIFI-BT-REV%20B.pdf PINE A64 Wifi/BT Module Schematic]
* SOEdge module together with model "A" baseboard Certification:
** Disclaimer: Please note that SOEdge module is not a "final" product and in general certification is not necessary. However, SOEdge module still submits the mpdel A baseboard for FCC, CE, and ROHS certifications and obtain the certificates to prove that can pass the testing. Please note, a final commercial product needs to perform its own testing and obtain its own certificate.
** Not yet available
** Not yet available


== Datasheets for Components and Peripherals ==
== Datasheets for Components and Peripherals ==
* Rockchip RK1808 SoC information:
* Rockchip RK3566 SoC information:
** [https://opensource.rock-chips.com/images/4/43/Rockchip_RK1808_Datasheet_V1.2_20190527.pdf Rockchip RK1808 ver 1.2 datasheet]
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
** [https://files.pine64.org/doc/datasheet/SOEdge/Rockchip%20RK1808%20TRM%20Part1%20V1.2--20190826%20open%20source.pdf Rockchip TK1808 Technical Reference Manual Part 1]
* LPDDR4 (200 Balls) SDRAM:
* Rockchip RK809 PMU (Power Management Unit) information:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
** [https://rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 PMIC Datasheet]
* DDR4 information:
** [https://files.pine64.org/doc/datasheet/SOEdge/Micron%208Gb_DDR4_SDRAM.pdf Micron DDR4 Datasheet]
* eMMC information:
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
Line 102: Line 98:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* '''SOEdge Related:'''
* E-ink Panel information:
** 5MPixel CMOS Camera module information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
*** [https://files.pine64.org/doc/datasheet/pine64/YL-PINE64-4EC.pdf PINE64 YL-PINE64-4EC 5M Pixel CMOS Image Sensor Module (Description in Chinese)]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
*** [https://files.pine64.org/doc/datasheet/pine64/S5K4EC%205M%208%205X8%205%20PLCC%20%20Data%20Sheet_V1.0.pdf S5K4EC 5MP CMOS Image Sensor SoC Module Datasheet]
* LCD Touch Screen Panel information:
*** [https://files.pine64.org/doc/datasheet/pine64/S5K4ECGX_EVT1_DataSheet_R005_20100816.pdf S5K4EC 5MP CMOS Image Sensor SoC Chip Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
*** [https://files.pine64.org/doc/datasheet/pine64/s5k4ec.c S5K4EC 5MP CMOS Image Sensor Driver Source Code in C language]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
*** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
* Ethernet PHY information:
*** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
*** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* WiFi/BT module info:
** Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/rockpro64/AP6256%20datasheet_V1.3_12202017.pdf AMPAK AP6256 11AC WiFi + Bluetooth5.0 Datasheet]]
*** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver for SOEdge model A baseboard]
* Enclosure information:
** Wifi/BT module information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
*** [https://files.pine64.org/doc/Pine%20A64%20Schematic/A64-DB-WIFI-BT-REV%20B.pdf SOEdge/SOPine/PINE A64 Wifi/BT Module Schematic]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
*** [https://files.pine64.org/doc/datasheet/pine64/RTL8723BS.pdf Realtek RTL8723BS WiFi with BT SDIO]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
** Enclosure information:
* Connector information:
*** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port]
*** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]
*** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
 
** Connector information:
== Android SDK ==
*** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port]
*** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]


== SOEdge/SOPine Cluster Board Resource ==
=== Android 11 SDK  ===
* Cluster board is an hardware open source project and will be available at PINE64 store on late January 2018.
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
* Please note that this project is not "OSH" compliance.:
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** [https://files.pine64.org/doc/clusterboard/PINE64%20CLUSTER%20BOARD_2_2.DSN Clusterboard version 2.2 Schematic Capture source file]
** File Size: 79.00GB
** [https://files.pine64.org/doc/clusterboard/PINE64%20CLUSTER%20BOARD_2_2_Schematic.pdf Clusterboard version 2.2 Schematic Capture PDF file]
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]
** [https://files.pine64.org/doc/clusterboard/PINE64%20CLUSTER%20BOARD_2_2.brd Clusterboard version 2.2 PCB Job source file]
** [https://files.pine64.org/doc/clusterboard/PINE64%20CLUSTER%20BOARD%20V2.2-gerber.rar Clusterboard version 2.2 PCB Gerber file]
** [https://files.pine64.org/doc/clusterboard/PINE64%20CLUSTER%20BOARD_2_2_PCB.pdf Clusterboard version 2.2 PCB Layout PDF file]
** [https://files.pine64.org/doc/clusterboard/clusterboard_20pins_header.jpg Clusterboard 20pins header definition]
** [https://myhub.autodesk360.com/ue2b2f72e/g/shares/SH56a43QTfd62c1cd96840f4ec37c60bcf12 Clusterboard 3D drawing in Fusion360]
** [https://myhub.autodesk360.com/ue2b2f72e/g/shares/SH56a43QTfd62c1cd968cd6bc203ac753401?viewState=NoIgbgDAdAjCA0ICGBmARgEwGZIOwGMBaDFADgFNCAWfAJi2o1IFZDmlTSIA2DW8-FTQgAukA Clusterboard PDF drawing]


== Other Resources ==
== Other Resources ==
Line 141: Line 129:




[[Category:Quartz]]
[[Category:Quartz64]]

Revision as of 20:01, 21 February 2021

The Quartz64 is the most recent Single Board Computer offering from Pine64, scheduled for release in 2021. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 is equipped with 2GB, 4GB or 8GB LPDDR4 system memory, and 128Mb SPI boot Flash. There is also an optional eMMC module (up to 128GB) and microSD slot for booting. The board is equipped with 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, eink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

Software and OS Image Downloads

  • TBD

SoC and Memory Specification

RK3566 icon.png

CPU Architecture

  • Quad-core ARM Cortex-A55 CPU
  • AArch32 for full backward compatibility with Armv7
  • ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
  • Include VFP hardware to support single and double-precision operations
  • ARMv8 Cryptography Extensions
  • Integrated 32KB L1 instruction cache, 32KB L1 data cache
  • 512KB unified system L3 cache
  • TrustZone technology support

Graphic Process Unit GPU Capability

  • Mali-G52 2EE Bifrost GPU@800MHz
  • 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
  • 128KB L2 Cache configurations
  • Support OpenGL ES 1.1, 2.0, and 3.2
  • Support Vulkan 1.0 and 1.1
  • Support OpenCL 2.0 Full Profile
  • Support 1600Mpix/s fill rate when 800MHz clock frequency
  • Support 38.4GLOPs when 800MHz clock frequency

Neural Process Unit NPU Capability

  • Neural network acceleration engine with processing performance up to 0.8 TOPS
  • Support integer 8, integer 16 convolution operation
  • Support deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

System Memory

  • RAM Memory Variants: 2GB - 8GB LPDDR4.
  • SPI Flash: 128Mbit / 16MByte

Network

  • 10/100/1000Mbps Ethernet
  • WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, build in on model B)

Storage

  • microSD - bootable, supports SDHC and SDXC, storage up to 2TB
  • USB - 2 ports on model B, 3 ports on model A USB 2.0 Host port, 1 USB 3.0 Host port
  • one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
  • optional eMMC module from 16GB up to 128GB

Expansion Ports

  • eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
  • DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
  • CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
  • TP - Touch Panel Port, SPI with interrupt on model A
  • RTC - Real Time Clock Battery Connector
  • VBAT - Lithium Battery Connector with temperature sensor input on model A
  • Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
  • 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
  • PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints

Quartz64 board Information, Schematics, and Certifications

  • Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
  • Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector
  • Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
  • Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID Barrel DC Jack connector
  • Certification:
    • Not yet available


Datasheets for Components and Peripherals

Android SDK

Android 11 SDK

Other Resources