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The Ox64
Pinout of the production version
Powered by RISC-V

The Ox64 is a RISC-V based Single Board Computer powered by Bouffalo Lab BL808 C906 64-Bit RISC-V CPU, 32-Bit CPU, embedded 64MB PSRAM memory and build-on 3 radio RF (Wifi, BT, Zigbee). It provides breadboard friendly form factor, MicroSD Card slot, USB 2.0, and many other peripheral interfaces for makers to integrate with sensors and other devices.

Software Releases

Quick Links to the Source of OS Images Build

There is a community effort to bring updated kernels, peripherals and buildroot - Lots of communication happening in the #ox64-nutcracker channel.

  • buildroot bringing all the work below together with a bootable kernel and updated filesystem images for SD cards
  • U-Boot and OpenSBI work by Smauel
  • Kernel IRQChip, SDCard, and (WIP) USB by arm000, Alexander Horner and others
  • OpenBouffalo Firmware low_load drivers by Fishwaldo and others

Original Linux Images provided by Bouffalo - Very basic alpha build which are only fit for board bring up and testing purposes.


  • elf_newlib_toolchain/bin/riscv64-unknown-elf-gcc (Xuantie-900 elf newlib gcc Toolchain V2.2.5 B-20220323) 10.2.0
  • linux_toolchain/bin/riscv64-unknown-linux-gnu-gcc (Xuantie-900 linux-5.10.4 glibc gcc Toolchain V2.2.4 B-20211227) 10.2.0
  • cmake version 3.19.3

Software Development Kits

SoC and Memory Specification

Bouffalo Lab icon.png

Based on the Bouffalo Lab BL808

BL808 Block Diagram.jpg

CPU Architecture


T-Head C906 480MHz 64-bit RISC-V CPU:

  • Supports RISC-V RV64IMAFCV instruction architecture
  • Five-stage single-issue sequentially executed pipeline
  • Level-1 instruction and data cache of Harvard architecture, with a size of 32 KB and a cache line of 64B
  • Sv39 memory management unit, realizing the conversion of virtual and real addresses and memory management
  • jTLB that supports 128 entries
  • Supports AXI 4.0 128-bit master interface
  • Supports core local interrupt (CLINT) and platform-level interrupt controller (PLIC)
  • With 80 external interrupt sources, 3 bits for configuring interrupt priority
  • Supports BHT (8K) and BTB
  • Compatible with RISC-V PMP, 8 configurable areas
  • Supports hardware performance monitor (HPM) units
  • See here

T-Head E907 320MHz 32-bit RISC-V CPU:

  • Supports RISC-V RV32IMAFCP instruction set
  • Supports RISC-V 32-bit/16-bit mixed instruction set
  • Supports RISC-V machine mode and user mode
  • Thirty-two 32-bit integer general purpose registers (GPR) and thirty-two 32-bit/64-bit floating-point GPRs
  • Integer (5-stage)/floating-point (7-stage), single-issue, sequentially executed pipeline
  • Supports AXI 4.0 main device interface and AHB 5.0 peripheral interface
  • 32K instruction cache, two-way set associative structure
  • 16K data cache, two-way set associative structure
  • See here

T-Head E902 150MHz 32-bit RISC-V CPU:

System Memory

  • Embedded 64MB PSRAM

Board Features


  • 2.4GHz 1T1R WiFi 802.11 b/g/n
  • Bluetooth 5.2
  • Zigbee
  • 10/100Mbps Ethernet (optional, on expansion board)


  • On-board 16Mb (2MB) or 128Mb (16MB) XSPI NOR flash memory
  • MicroSD - supports SDHC and SDXC (only 128Mb version)

Expansion Ports

  • USB 2.0 OTG port
  • 26 GPIO Pins, including SPI, I2C and UART functionality. Possible I2S and GMII expansion
  • Dual lane MiPi CSI port, located at USB-C port, for camera module


  • Microphone (optional, on camera module)
  • Speaker (optional, on camera module)

Board Information, Schematics and Certifications

Pinout for wiring ethernet PHY to EMAC
  • Baseboard Dimensions: 51mm x 21mm x 19mm x 3.5mm (Breadboard friendly)
  • Input Power: 5V 0.5A microUSB or USB-C port

Production version schematic:

Prototype (dispatched to developers) schematic:


  • Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary.
  • Not yet available

Datasheets for Components and Peripherals

Bouffalo BL808 SoC information:

SPI NOR Flash information:

Power Regulator information:

MicroSD socket information:

Compatible UARTs when in bootloader mode

When the Ox64 is in bootloader mode, some UARTs are unable to communicate with it. When this is the case, utilities such as BLDevCube are unable to actually program the device. If you see "Shake hand fail" and an empty ack, and your device is in bootloader mode, then it is likely an incompatible UART.

The below devices have been tested and verified as working:

  • Raspberry Pi Pico - running the following UART firmware (GP4 and GP5 are used for port 0, GP12 and GP13 for port 1)
  • Compiled binary for Pi Pico and connectivity diagram is here
  • ESP32 with CP210x - bridge the EN pin to ground to disable the ESP32 itself, and then connect the TX on the esp32 to 14 on the Ox64 and RX to pin 15. Note that only baud rate 115200 works, and this doesn't seem to work for everyone)
  • Stand-alone CP2102 dongle works at 115200 baud. Brand used was HiLetgo.
  • STM32F401 BlackPill - running the Black Magic Debug firmware
  • STM32F103C8T6 BluePill - running Black Magic Debug.
  • Some UART adapters based on the FT232H (note that the FT232RL does not work, and neither does the Pine 64 JTAG)
  • Some CH340G based adapters work and some don't.


Git repositories:

Development Efforts