Difference between revisions of "Ox64"

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=== Quick Links to the Source of OS Images Build ===
=== Quick Links to the Source of OS Images Build ===


OS images are still in '''alpha build''' which are only fit for board bring up and testing purposes.  
There is a community effort to bring updated kernels, peripherals and buildroot - Lots of communication happening in the #ox64-nutcracker channel.
 
* [https://github.com/openbouffalo/buildroot_bouffalo buildroot] bringing all the work below together with a bootable kernel and updated filesystem images for SD cards
* [https://github.com/smaeul/u-boot/tree/bl808 U-Boot] and [https://github.com/smaeul/opensbi/tree/bl808 OpenSBI] work by Smauel
* [https://github.com/arm000/linux-bl808/tree/linux-next/mboxic Kernel] IRQChip, SDCard, and (WIP) USB by arm000, Alexander Horner and others
* [https://github.com/openbouffalo/OBLFR OpenBouffalo Firmware] low_load drivers by Fishwaldo and others
 
Original Linux Images provided by Bouffalo - Very basic '''alpha build''' which are only fit for board bring up and testing purposes.  


* [https://github.com/bouffalolab/bl808_linux Linux for BL808]
* [https://github.com/bouffalolab/bl808_linux Linux for BL808]
Line 29: Line 36:
* [https://github.com/bouffalolab/bl808-pac Rust Peripheral Access Crate (PAC) for BL808]
* [https://github.com/bouffalolab/bl808-pac Rust Peripheral Access Crate (PAC) for BL808]
* [https://github.com/bouffalolab/bl808-pac/blob/main/bl808.svd System View Description (SVD) for BL808]
* [https://github.com/bouffalolab/bl808-pac/blob/main/bl808.svd System View Description (SVD) for BL808]


== SoC and Memory Specification ==
== SoC and Memory Specification ==
Line 35: Line 41:
[[File:Bouffalo_Lab_icon.png|right]]
[[File:Bouffalo_Lab_icon.png|right]]
[[File:BL808_Block_Diagram.jpg|600px]]
[[File:BL808_Block_Diagram.jpg|600px]]


=== CPU Architecture ===
=== CPU Architecture ===
* [https://www.t-head.cn/product/c906?lang=en T_head C906 480MHz 64-bit RISC-V CPU]
[[File:T-Head.png|right|200px]]
[[File:T-Head.png|right|200px]]
** Supports RISC-V RV64IMAFCV instruction architecture
** Five-stage single-issue sequentially executed pipeline
** Level-1 instruction and data cache of Harvard architecture, with a size of 32 KB and a cache line of 64B
** Sv39 memory management unit, realizing the conversion of virtual and real addresses and memory management
** jTLB that supports 128 entries
** Supports AXI 4.0 128-bit master interface
** Supports core local interrupt (CLINT) and platform-level interrupt controller (PLIC)
** With 80 external interrupt sources, 3 bits for configuring interrupt priority
** Supports BHT (8K) and BTB
** Compatible with RISC-V PMP, 8 configurable areas
** Supports hardware performance monitor (HPM) units


* [https://www.t-head.cn/product/e907?lang=en T_head E907 320MHz 32-bit RISC-V CPU]
[https://www.t-head.cn/product/c906?lang=en T-Head C906 480MHz 64-bit RISC-V CPU]:
** Supports RISC-V RV32IMAFCP instruction set
* Supports RISC-V RV64IMAFCV instruction architecture
** Supports RISC-V 32-bit/16-bit mixed instruction set
* Five-stage single-issue sequentially executed pipeline
** Supports RISC-V machine mode and user mode
* Level-1 instruction and data cache of Harvard architecture, with a size of 32 KB and a cache line of 64B
** Thirty-two 32-bit integer general purpose registers (GPR) and thirty-two 32-bit/64-bit floating-point GPRs
* Sv39 memory management unit, realizing the conversion of virtual and real addresses and memory management
** Integer (5-stage)/floating-point (7-stage), single-issue, sequentially executed pipeline
* jTLB that supports 128 entries
** Supports AXI 4.0 main device interface and AHB 5.0 peripheral interface
* Supports AXI 4.0 128-bit master interface
** 32K instruction cache, two-way set associative structure
* Supports core local interrupt (CLINT) and platform-level interrupt controller (PLIC)
** 16K data cache, two-way set associative structure
* With 80 external interrupt sources, 3 bits for configuring interrupt priority
* Supports BHT (8K) and BTB
* Compatible with RISC-V PMP, 8 configurable areas
* Supports hardware performance monitor (HPM) units


[https://www.t-head.cn/product/e907?lang=en T-Head E907 320MHz 32-bit RISC-V CPU]:
* Supports RISC-V RV32IMAFCP instruction set
* Supports RISC-V 32-bit/16-bit mixed instruction set
* Supports RISC-V machine mode and user mode
* Thirty-two 32-bit integer general purpose registers (GPR) and thirty-two 32-bit/64-bit floating-point GPRs
* Integer (5-stage)/floating-point (7-stage), single-issue, sequentially executed pipeline
* Supports AXI 4.0 main device interface and AHB 5.0 peripheral interface
* 32K instruction cache, two-way set associative structure
* 16K data cache, two-way set associative structure
[https://www.t-head.cn/product/e902?lang=en T-Head E902 150MHz 32-bit RISC-V CPU]:


=== System Memory ===
=== System Memory ===
Line 76: Line 83:
=== Storage ===
=== Storage ===
* on-board 16Mb (2MB) or 128Mb (16MB) XSPI NOR flash memory
* on-board 16Mb (2MB) or 128Mb (16MB) XSPI NOR flash memory
* microSD - supports SDHC and SDXC
* microSD - supports SDHC and SDXC (only 128Mb version)


=== Expansion Ports ===
=== Expansion Ports ===
Line 87: Line 94:
* speaker (optional, on camera module)
* speaker (optional, on camera module)


== Board Information, Schematics and Certifications ==
[[file:0x64pinout.png|500px|thumb|Pinout of the production version]]
[[file:0x64pinout-ethphy.png|500px|thumb|Pinout for wiring ethernet PHY to EMAC]]


== Board Information, Schematics and Certifications ==
* Baseboard Dimensions: 51mm x 21mm x 19mm x 3.5mm (Breadboard friendly)
* Baseboard Dimensions: 51mm x 21mm x 19mm x 3.5mm (Breadboard friendly)
* Input Power: 5V 0.5A microSD or USB-C port
* Input Power: 5V 0.5A microUSB or USB-C port
* Schematic:
=== Production version schematic: ===
** [https://files.pine64.org/doc/ox64/PINE64_Ox64-Schematic-202221018.pdf Ox64 Schematic 20221018 v1.1]
** [https://files.pine64.org/doc/ox64/PINE64_Ox64_PCB_Placement-Top-20221018.pdf Ox64 PCB Component placement(ToP) 20221018 v1.1]
** [https://files.pine64.org/doc/ox64/PINE64_Ox64_PCB_Placement-Bottom-20221018.pdf Ox64 PCB Component placement(Bottom) 20221018 v1.1]
=== Prototype (dispatched to developers) schematic: ===
** [https://files.pine64.org/doc/ox64/PINE64_Ox64-Schematic-202221007.pdf Ox64 Schematic 20221007 v1.0]
** [https://files.pine64.org/doc/ox64/PINE64_Ox64_PCB_Placement-Top-20221007.pdf Ox64 PCB Component placement(ToP) 20221007 v1.0]
** [https://files.pine64.org/doc/ox64/PINE64_Ox64_PCB_Placement-Bottom-20221007.pdf Ox64 PCB Component placement(Bottom) 20221007 v1.0]


* Certifications:
Production version schematic:
** Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary.
 
** Not yet available
* [https://files.pine64.org/doc/ox64/PINE64_Ox64-Schematic-202221018.pdf Ox64 Schematic 20221018 v1.1]
* [https://files.pine64.org/doc/ox64/PINE64_Ox64_PCB_Placement-Top-20221018.pdf Ox64 PCB Component placement(ToP) 20221018 v1.1]
* [https://files.pine64.org/doc/ox64/PINE64_Ox64_PCB_Placement-Bottom-20221018.pdf Ox64 PCB Component placement(Bottom) 20221018 v1.1]
 
Prototype (dispatched to developers) schematic:
* [https://files.pine64.org/doc/ox64/PINE64_Ox64-Schematic-202221007.pdf Ox64 Schematic 20221007 v1.0]
* [https://files.pine64.org/doc/ox64/PINE64_Ox64_PCB_Placement-Top-20221007.pdf Ox64 PCB Component placement(ToP) 20221007 v1.0]
* [https://files.pine64.org/doc/ox64/PINE64_Ox64_PCB_Placement-Bottom-20221007.pdf Ox64 PCB Component placement(Bottom) 20221007 v1.0]
 
Certifications:
* Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary.
* Not yet available


== Datasheets for Components and Peripherals ==
== Datasheets for Components and Peripherals ==
* Bouffalo BL808 SoC information:
 
** [https://files.pine64.org/doc/datasheet/ox64/BL808_DS_en_1.1(open).pdf Bouffalo Lab BL808 SoC Datasheet]
Bouffalo BL808 SoC information:
** [https://files.pine64.org/doc/datasheet/ox64/BL808_RM_en_1.0(open).pdf Bouffalo Lab BL808 SoC Reference Manual]
* [https://files.pine64.org/doc/datasheet/ox64/BL808_DS_en_1.1(open).pdf Bouffalo Lab BL808 SoC Datasheet]
* SPI NOR Flash information:
* [https://raw.githubusercontent.com/bouffalolab/bl_docs/main/BL808_RM/en/BL808_RM_en_1.2.pdf Bouffalo Lab BL808 SoC Reference Manual]
** [https://files.pine64.org/doc/datasheet/ox64/gd25lq16e_rev1.2_20210108.pdf GigaDevice 16Mb XSPI-Flash Datasheet]
 
** [https://files.pine64.org/doc/datasheet/star64/gd25lq128e_rev1.0_20210513.pdf GigaDevice 128Mb XSPI-Flash Datasheet]
SPI NOR Flash information:
* Power Regulator information:
* [https://files.pine64.org/doc/datasheet/ox64/gd25lq16e_rev1.2_20210108.pdf GigaDevice 16Mb XSPI-Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/ox64/IA2014-03.pdf Innovation Analog Tech IA2014 Step_down Converter Datasheet]
* [https://files.pine64.org/doc/datasheet/star64/gd25lq128e_rev1.0_20210513.pdf GigaDevice 128Mb XSPI-Flash Datasheet]
* MicroSD socket information:
 
** [https://files.pine64.org/doc/datasheet/ox64/TF%20PUSH%20type%20socket%20specification.pdf Push type microSD socket specification]
Power Regulator information:
* [https://files.pine64.org/doc/datasheet/ox64/IA2014-03.pdf Innovation Analog Tech IA2014 Step_down Converter Datasheet]
 
MicroSD socket information:
* [https://files.pine64.org/doc/datasheet/ox64/TF%20PUSH%20type%20socket%20specification.pdf Push type microSD socket specification]


== Compatible UARTs when in bootloader mode ==
== Compatible UARTs when in bootloader mode ==
* When the Ox64 is in bootloader mode, some UARTs are unable to communicate with it. When this is the case, utilities such as BLDevCube are unable to actually program the device.
* If you see "Shake hand fail" and an empty ack, and your device is in bootloader mode, then it is likely an incompatible UART.
* The below devices have been tested and verified as working
** Raspberry Pi Pico - running a modified version of [https://github.com/sanjay900/picoprobe/releases/tag/v1.0 picoprobe]
** Adapters based on the CP2102
*** This also includes ESP32s with this chip on board, bridge the EN pin to ground to disable the ESP32 itself, and then connect the TX on the esp32 to 14 on the Ox64 and RX to pin 15
** Some UART adapters based on the FT232H (note that the FT232RL does not work, and neither does the Pine 64 JTAG)
** Some CH340G based adapters work and some don't.


== GitHub/Gitlab ==
When the Ox64 is in bootloader mode, some UARTs are unable to communicate with it. When this is the case, utilities such as BLDevCube are unable to actually program the device. If you see "Shake hand fail" and an empty ack, and your device is in bootloader mode, then it is likely an incompatible UART.
* [https://github.com/bouffalolab/bl808-pac Official Bouffalo BL-808 site]
 
* [https://github.com/sfranzyshen/arduino-bl808 Community made Arduino Core specifically for the Bouffalo Labs BL808 RISC-V MCU]
The below devices have been tested and verified as working:
* Raspberry Pi Pico - running the following [https://github.com/sanjay900/ox64-uart/releases/tag/v1.1 uart firmware] (GP4 and GP5 are used for port 0, GP12 and GP13 for port 1)
* Compiled binary for Pi Pico and connectivity diagram is [https://github.com/Kris-Sekula/Pine64_Ox64_SBC/tree/main/uart here]
* ESP32 with CP210x - bridge the EN pin to ground to disable the ESP32 itself, and then connect the TX on the esp32 to 14 on the Ox64 and RX to pin 15. Note that only baud rate 115200 works, and this doesn't seem to work for everyone)
* Stand-alone CP2102 dongle works at 115200 baud. Brand used was HiLetgo.
* STM32F401 BlackPill - running the [https://github.com/blackmagic-debug/blackmagic/tree/main/src/platforms/blackpillv2 Black Magic Debug] firmware
* STM32F103C8T6 BluePill - running Black Magic Debug.
* Some UART adapters based on the FT232H (note that the FT232RL does not work, and neither does the Pine 64 JTAG)
* Some CH340G based adapters work and some don't.


== Articles and Blogs ==
== Resources ==
* A video on how to connect to, flash and boot the Ox64 as at 2023-02 (15min) can be found [https://youtube.com/watch?v=czRtF-UNiEY here].
* Another video that covers soldering pins, connecting via Pi Pico and flashing Linux (inc u-boot, as of 2023-Mar-3) posted [https://youtu.be/vPAk5sq_Ilc here].
* [https://gist.github.com/lupyuen/7a0c697b89abccda8e38b33dfe5ebaff First Batch of Ox64 won't appear as USB Serial Port]
* [https://gist.github.com/lupyuen/7a0c697b89abccda8e38b33dfe5ebaff First Batch of Ox64 won't appear as USB Serial Port]
* [https://gist.github.com/lupyuen/2087e9b3fb40aab5e0795bb02a265a3b First Batch of Ox64 tested OK with CH340C/G]
* [https://gist.github.com/lupyuen/2087e9b3fb40aab5e0795bb02a265a3b First Batch of Ox64 tested OK with CH340C/G]
* [https://www.robertlipe.com/bl808-not-symmetric/ First thoughts on the (a)symmetry of Bouffalo Labs BL808 as in Pine64’s Ox64]
* [https://www.robertlipe.com/bl808-not-symmetric/ First thoughts on the (a)symmetry of Bouffalo Labs BL808 as in Pine64’s Ox64]
* [https://thelittleengineerthatcould.blogspot.com/2022/12/the-8-linux-computer-part-2.html The $8 linux computer (with picoprobe-rp2040 programming instructions)]
* [https://github.com/p4ddy1/pine_ox64/blob/main/build_toolchain_macos.md Building the Xuantie GNU Toolchain for Ox64 on macOS and Apple Silicon]
Git repositories:
* [https://github.com/bouffalolab/bl808-pac Official Bouffalo BL-808 site]
* [https://github.com/sfranzyshen/arduino-bl808 Community made Arduino Core specifically for the Bouffalo Labs BL808 RISC-V MCU] (Initial development has been postponed until further notice.)


== Development Efforts ==
== Development Efforts ==
Line 140: Line 163:
* [https://twitter.com/btashton/status/1586381334439923713?t=w5xRRUR74HGK2O1Zg_aFyw&s=19 Brennan Ashton is porting Apache NuttX RTOS and OpenAMP (Asymmetric Multiprocessing) to BL808]
* [https://twitter.com/btashton/status/1586381334439923713?t=w5xRRUR74HGK2O1Zg_aFyw&s=19 Brennan Ashton is porting Apache NuttX RTOS and OpenAMP (Asymmetric Multiprocessing) to BL808]
* [https://twitter.com/thanos_engine/status/1585153938092761093 Phone Concept for BL808]
* [https://twitter.com/thanos_engine/status/1585153938092761093 Phone Concept for BL808]


[[Category:Ox64]] [[Category:Bouffalo BL808]]
[[Category:Ox64]] [[Category:Bouffalo BL808]]

Revision as of 09:22, 3 March 2023

The Ox64

The Ox64 is a RISC-V based Single Board Computer powered by Bouffalo Lab BL808 C906 64-Bit RISC-V CPU, 32-Bit CPU, embedded 64MB PSRAM memory and build-on 3 radio RF (Wifi, BT, Zigbee). It provides breadboard friendly form factor, MicroSD Card slot, USB 2.0, and many other peripheral interfaces for makers to integrate with sensors and other devices.

RISC-V.png

Software Releases

Quick Links to the Source of OS Images Build

There is a community effort to bring updated kernels, peripherals and buildroot - Lots of communication happening in the #ox64-nutcracker channel.

  • buildroot bringing all the work below together with a bootable kernel and updated filesystem images for SD cards
  • U-Boot and OpenSBI work by Smauel
  • Kernel IRQChip, SDCard, and (WIP) USB by arm000, Alexander Horner and others
  • OpenBouffalo Firmware low_load drivers by Fishwaldo and others

Original Linux Images provided by Bouffalo - Very basic alpha build which are only fit for board bring up and testing purposes.

Software Development Kits

SoC and Memory Specification

Bouffalo Lab icon.png

BL808 Block Diagram.jpg

CPU Architecture

T-Head.png

T-Head C906 480MHz 64-bit RISC-V CPU:

  • Supports RISC-V RV64IMAFCV instruction architecture
  • Five-stage single-issue sequentially executed pipeline
  • Level-1 instruction and data cache of Harvard architecture, with a size of 32 KB and a cache line of 64B
  • Sv39 memory management unit, realizing the conversion of virtual and real addresses and memory management
  • jTLB that supports 128 entries
  • Supports AXI 4.0 128-bit master interface
  • Supports core local interrupt (CLINT) and platform-level interrupt controller (PLIC)
  • With 80 external interrupt sources, 3 bits for configuring interrupt priority
  • Supports BHT (8K) and BTB
  • Compatible with RISC-V PMP, 8 configurable areas
  • Supports hardware performance monitor (HPM) units

T-Head E907 320MHz 32-bit RISC-V CPU:

  • Supports RISC-V RV32IMAFCP instruction set
  • Supports RISC-V 32-bit/16-bit mixed instruction set
  • Supports RISC-V machine mode and user mode
  • Thirty-two 32-bit integer general purpose registers (GPR) and thirty-two 32-bit/64-bit floating-point GPRs
  • Integer (5-stage)/floating-point (7-stage), single-issue, sequentially executed pipeline
  • Supports AXI 4.0 main device interface and AHB 5.0 peripheral interface
  • 32K instruction cache, two-way set associative structure
  • 16K data cache, two-way set associative structure

T-Head E902 150MHz 32-bit RISC-V CPU:

System Memory

  • Embedded 64MB PSRAM

Board Features

Network

  • 2.4GHz 1T1R WiFi 802.11 b/g/n
  • Bluetooth 5.2
  • Zigbee
  • 10/100Mbps Ethernet (optional, on expansion board)

Storage

  • on-board 16Mb (2MB) or 128Mb (16MB) XSPI NOR flash memory
  • microSD - supports SDHC and SDXC (only 128Mb version)

Expansion Ports

  • USB 2.0 OTG port
  • 26 GPIO Pins, including SPI, I2C and UART functionality. Possible I2S and GMII expansion
  • Dual lane MiPi CSI port, located at USB-C port, for camera module

Audio

  • mic (optional, on camera module)
  • speaker (optional, on camera module)

Board Information, Schematics and Certifications

Pinout of the production version
Pinout for wiring ethernet PHY to EMAC
  • Baseboard Dimensions: 51mm x 21mm x 19mm x 3.5mm (Breadboard friendly)
  • Input Power: 5V 0.5A microUSB or USB-C port

Production version schematic:

Prototype (dispatched to developers) schematic:

Certifications:

  • Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary.
  • Not yet available

Datasheets for Components and Peripherals

Bouffalo BL808 SoC information:

SPI NOR Flash information:

Power Regulator information:

MicroSD socket information:

Compatible UARTs when in bootloader mode

When the Ox64 is in bootloader mode, some UARTs are unable to communicate with it. When this is the case, utilities such as BLDevCube are unable to actually program the device. If you see "Shake hand fail" and an empty ack, and your device is in bootloader mode, then it is likely an incompatible UART.

The below devices have been tested and verified as working:

  • Raspberry Pi Pico - running the following uart firmware (GP4 and GP5 are used for port 0, GP12 and GP13 for port 1)
  • Compiled binary for Pi Pico and connectivity diagram is here
  • ESP32 with CP210x - bridge the EN pin to ground to disable the ESP32 itself, and then connect the TX on the esp32 to 14 on the Ox64 and RX to pin 15. Note that only baud rate 115200 works, and this doesn't seem to work for everyone)
  • Stand-alone CP2102 dongle works at 115200 baud. Brand used was HiLetgo.
  • STM32F401 BlackPill - running the Black Magic Debug firmware
  • STM32F103C8T6 BluePill - running Black Magic Debug.
  • Some UART adapters based on the FT232H (note that the FT232RL does not work, and neither does the Pine 64 JTAG)
  • Some CH340G based adapters work and some don't.

Resources

Git repositories:

Development Efforts