Difference between revisions of "PineCone"

Revision as of 02:26, 26 November 2020

Page under construction, information subject to change.

CPU: 32-bit RV32IMAFC RISC-V “SiFive E24 Core”
- SiFive E24 Core information
Memory:
- 128KB ROM
- 276KB SRAM
- 1Kb eFuse
- 2MB Embedded Flash
Security:
- Secure boot
- Secure debug
- XIP QSPI On-The-Fly AES Decryption (OTFAD)
- AES 128/192/256
- SHA-1/224/256
- TRNG (True Random Number Generator)
- PKA (Public Key Accelerator)
Wireless:
- Wi-Fi 802.11 b/g/n
- Bluetooth® Low Energy 5.0
- Wi-Fi Fast connection with BLE assistance
- Wi-Fi and BLE coexistence
- Wi-Fi Security WPS/WEP/WPA/WPA2/WPA3
- STA, SoftAP and sniffer modes
- Multi-Cloud connectivity
- 2.4 GHz RF transceiver
- Integrated RF balun, PA/LNA
Package Type:
- 32 pin QFN 4mm x 4mm

PineCone BL602 EVB schematic ver 1.1
- Note: Current schematic, cc1 and cc2 share one 5.1KOhm resistor. Next schematic design will separate out the cc1 and cc2 has it own 5.1KOhm resistors

Bouffalo BL-602 SoC information:
- Bouffalo Lab BL602 SoC Datasheet V1.2
- Bouffalo Lab BL602 SoC Datasheet V1.1
- Bouffalo Lab BL602 SoC Reference Manual V1.1
  - Please note that the Chinese wording "寄存器描述" means "Register Description" in reference manual ver 1.1

Planned to be available in at least three form factors:

@@ Line 16: / Line 16: @@
 ** 276KB SRAM
 ** 1Kb eFuse
-** 4MB Embedded Flash
+** 2MB Embedded Flash
 * '''Security:'''
 ** Secure boot