Difference between revisions of "SOEDGE"
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=== CPU Architecture === | === CPU Architecture === | ||
* [ | * [https://www.arm.com/products/processors/cortex-a/cortex-a53-processor.php Dual-core ARM Cortex-A35 Processor@1600-2000Mhz] | ||
* A power-efficient ARM 64-Bit Armv8-A architecture | * A power-efficient ARM 64-Bit Armv8-A architecture | ||
* AArch32 for full backward compatibility with Armv7 | * AArch32 for full backward compatibility with Armv7 | ||
| Line 75: | Line 75: | ||
* SOEdge Module Schematic: | * SOEdge Module Schematic: | ||
** [ | ** [https://files.pine64.org/doc/SOEdge/SOEdge-Schematic-v2.0-190919.pdf SOEdge Module ver 2.0 20190919 Schematic] | ||
** [ | ** [https://files.pine64.org/doc/SOEdge/SoEdge-PCB-placement-v2.0-topplace.pdf SOEdge Module ver 2.0 20190919 PCB Component Placement Top PDF file] | ||
** [ | ** [https://files.pine64.org/doc/SOEdge/SoEdge-PCB-placement-v2.0-bottomplace.pdf SOEdge Module ver 2.0 20190919 PCB Component Placement Bottom PDF file] | ||
** [ | ** [https://files.pine64.org/doc/SOEdge/SoEdge-PCB-placement-v2.0-topplace.dxf SOEdge Module ver 2.0 20190919 PCB Component Placement Top Drawing file] | ||
** [ | ** [https://files.pine64.org/doc/SOEdge/SoEdge-PCB-placement-v2.0-bottomplace.dxf SOEdge Module ver 2.0 20190919 PCB Component Placement Bottom Drawing file] | ||
** [ | ** [https://files.pine64.org/doc/SOEdge/SOEdge%20Pin%20Assignments%20ver%201.00.xlsx SOEdge Module Pin Assignment ver 1.0 in Excel format(includes comparison chart to SOPine)] | ||
** [ | ** [https://files.pine64.org/doc/SOEdge/SOEdge%20Pin%20Assignments%20ver%201.00.ods SOEdge Module Pin Assignment ver 1.0 in Open Document format(includes comparison chart to SOPine)] | ||
* SOEdge Model "A" Baseboard Schematic and PCB Board Resource: | * SOEdge Model "A" Baseboard Schematic and PCB Board Resource: | ||
** [ | ** [https://files.pine64.org/doc/SOEdge/SoEdge_Baseboard%20Schematic%20Model%20A-20200513.pdf SOEdge Model "A" Baseboard Schematic 20200513 PDF file] | ||
** [ | ** [https://files.pine64.org/doc/SOEdge/SoEdge_Baseboard_PCB_layout_Model_A2020-05-31.pdf SOEdge Model "A" Baseboard PCB Layout PDF file] | ||
* SOEdge Neural AI Stick Schematic: | * SOEdge Neural AI Stick Schematic: | ||
** [ | ** [https://files.pine64.org/doc/SOEdge/SOEdge%20Neural%20AI%20Stick%20Schematic_V10.pdf SOEdge Neural AI Stick PDF file] | ||
* SOEdge/SOPine/PINE A64 Wifi/BT module Schematic | * SOEdge/SOPine/PINE A64 Wifi/BT module Schematic | ||
** [ | ** [https://files.pine64.org/doc/Pine%20A64%20Schematic/A64-DB-WIFI-BT-REV%20B.pdf PINE A64 Wifi/BT Module Schematic] | ||
* SOEdge module together with model "A" baseboard Certification: | * SOEdge module together with model "A" baseboard Certification: | ||
** Disclaimer: Please note that SOEdge module is not a "final" product and in general certification is not necessary. However, SOEdge module still submits the mpdel A baseboard for FCC, CE, and ROHS certifications and obtain the certificates to prove that can pass the testing. Please note, a final commercial product needs to perform its own testing and obtain its own certificate. | ** Disclaimer: Please note that SOEdge module is not a "final" product and in general certification is not necessary. However, SOEdge module still submits the mpdel A baseboard for FCC, CE, and ROHS certifications and obtain the certificates to prove that can pass the testing. Please note, a final commercial product needs to perform its own testing and obtain its own certificate. | ||
| Line 95: | Line 95: | ||
== Datasheets for Components and Peripherals == | == Datasheets for Components and Peripherals == | ||
* Rockchip RK1808 SoC information: | * Rockchip RK1808 SoC information: | ||
** [ | ** [https://opensource.rock-chips.com/images/4/43/Rockchip_RK1808_Datasheet_V1.2_20190527.pdf Rockchip RK1808 ver 1.2 datasheet] | ||
** [ | ** [https://files.pine64.org/doc/datasheet/SOEdge/Rockchip%20RK1808%20TRM%20Part1%20V1.2--20190826%20open%20source.pdf Rockchip TK1808 Technical Reference Manual Part 1] | ||
* Rockchip RK809 PMU (Power Management Unit) information: | * Rockchip RK809 PMU (Power Management Unit) information: | ||
** [https://rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 PMIC Datasheet] | ** [https://rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 PMIC Datasheet] | ||
* DDR4 information: | * DDR4 information: | ||
** [ | ** [https://files.pine64.org/doc/datasheet/SOEdge/Micron%208Gb_DDR4_SDRAM.pdf Micron DDR4 Datasheet] | ||
* eMMC information: | * eMMC information: | ||
** [ | ** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic] | ||
** [ | ** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic] | ||
** [ | ** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG] | ||
** [ | ** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet] | ||
** [ | ** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet] | ||
* SPI NOR Flash information: | * SPI NOR Flash information: | ||
** [ | ** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet] | ||
** [ | ** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet] | ||
* '''SOEdge Related:''' | * '''SOEdge Related:''' | ||
** 5MPixel CMOS Camera module information: | ** 5MPixel CMOS Camera module information: | ||
*** [ | *** [https://files.pine64.org/doc/datasheet/pine64/YL-PINE64-4EC.pdf PINE64 YL-PINE64-4EC 5M Pixel CMOS Image Sensor Module (Description in Chinese)] | ||
*** [ | *** [https://files.pine64.org/doc/datasheet/pine64/S5K4EC%205M%208%205X8%205%20PLCC%20%20Data%20Sheet_V1.0.pdf S5K4EC 5MP CMOS Image Sensor SoC Module Datasheet] | ||
*** [ | *** [https://files.pine64.org/doc/datasheet/pine64/S5K4ECGX_EVT1_DataSheet_R005_20100816.pdf S5K4EC 5MP CMOS Image Sensor SoC Chip Datasheet] | ||
*** [ | *** [https://files.pine64.org/doc/datasheet/pine64/s5k4ec.c S5K4EC 5MP CMOS Image Sensor Driver Source Code in C language] | ||
** LCD Touch Screen Panel information: | ** LCD Touch Screen Panel information: | ||
*** [ | *** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification] | ||
*** [ | *** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification] | ||
*** [ | *** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet] | ||
** Ethernet PHY information: | ** Ethernet PHY information: | ||
*** [ | *** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver for SOEdge model A baseboard] | ||
** Wifi/BT module information: | ** Wifi/BT module information: | ||
*** [ | *** [https://files.pine64.org/doc/Pine%20A64%20Schematic/A64-DB-WIFI-BT-REV%20B.pdf SOEdge/SOPine/PINE A64 Wifi/BT Module Schematic] | ||
*** [ | *** [https://files.pine64.org/doc/datasheet/pine64/RTL8723BS.pdf Realtek RTL8723BS WiFi with BT SDIO] | ||
** Enclosure information: | ** Enclosure information: | ||
*** [ | *** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file] | ||
*** [ | *** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file] | ||
*** [ | *** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing] | ||
** Connector information: | ** Connector information: | ||
*** [ | *** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port] | ||
*** [ | *** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port] | ||
== SOEdge/SOPine Cluster Board Resource == | == SOEdge/SOPine Cluster Board Resource == | ||
* Cluster board is an hardware open source project and will be available at PINE64 store on late January 2018. | * Cluster board is an hardware open source project and will be available at PINE64 store on late January 2018. | ||
* Please note that this project is not "OSH" compliance.: | * Please note that this project is not "OSH" compliance.: | ||
** [ | ** [https://files.pine64.org/doc/clusterboard/PINE64%20CLUSTER%20BOARD_2_2.DSN Clusterboard version 2.2 Schematic Capture source file] | ||
** [ | ** [https://files.pine64.org/doc/clusterboard/PINE64%20CLUSTER%20BOARD_2_2_Schematic.pdf Clusterboard version 2.2 Schematic Capture PDF file] | ||
** [ | ** [https://files.pine64.org/doc/clusterboard/PINE64%20CLUSTER%20BOARD_2_2.brd Clusterboard version 2.2 PCB Job source file] | ||
** [ | ** [https://files.pine64.org/doc/clusterboard/PINE64%20CLUSTER%20BOARD%20V2.2-gerber.rar Clusterboard version 2.2 PCB Gerber file] | ||
** [ | ** [https://files.pine64.org/doc/clusterboard/PINE64%20CLUSTER%20BOARD_2_2_PCB.pdf Clusterboard version 2.2 PCB Layout PDF file] | ||
** [ | ** [https://files.pine64.org/doc/clusterboard/clusterboard_20pins_header.jpg Clusterboard 20pins header definition] | ||
** [https://myhub.autodesk360.com/ue2b2f72e/g/shares/SH56a43QTfd62c1cd96840f4ec37c60bcf12 Clusterboard 3D drawing in Fusion360] | ** [https://myhub.autodesk360.com/ue2b2f72e/g/shares/SH56a43QTfd62c1cd96840f4ec37c60bcf12 Clusterboard 3D drawing in Fusion360] | ||
** [https://myhub.autodesk360.com/ue2b2f72e/g/shares/SH56a43QTfd62c1cd968cd6bc203ac753401?viewState=NoIgbgDAdAjCA0ICGBmARgEwGZIOwGMBaDFADgFNCAWfAJi2o1IFZDmlTSIA2DW8-FTQgAukA Clusterboard PDF drawing] | ** [https://myhub.autodesk360.com/ue2b2f72e/g/shares/SH56a43QTfd62c1cd968cd6bc203ac753401?viewState=NoIgbgDAdAjCA0ICGBmARgEwGZIOwGMBaDFADgFNCAWfAJi2o1IFZDmlTSIA2DW8-FTQgAukA Clusterboard PDF drawing] | ||
Revision as of 22:14, 28 October 2020
Software and OS Image Downloads
SOEdge Software Release
The SOEdge software releases can be found in the article SOEdge Software Release.
Accessories Step-by-Step Guides
Under 'Guides for model A baseboard accessories' you can find instructions and guides concerning:
- Enclosures
- Bluetooth and WiFi module
- Real Time Clock (RTC) battery
- Real Time Clock (RTC) battery holder
- First and third party cases
- Featured 3D printed cases (and more)
SoC and Memory Specification
- Based on Rockchip RK1808
CPU Architecture
- Dual-core ARM Cortex-A35 Processor@1600-2000Mhz
- A power-efficient ARM 64-Bit Armv8-A architecture
- AArch32 for full backward compatibility with Armv7
- Support NEON Advanced SIMD (Single Instruction Multiple Data) instruction for acceleration of media and signal processing function
- Support Large Physical Address Extensions(LPAE)
- VFPv4 Floating Point Unit
- 32KB L1 Instruction cache and 32KB L1 Data cache
- AArch64 for 64-bit support and new architectural features
- TrustZone security technology
- Neon Advanced SIMD
- DSP and SIMD extensions
- VFPv4 Floating point
- Hardware virtualization support
- 128KB L2 cache
Neural Process Unit NPU Capability
- NPU IP from Verisilicon Vivantee
- Support max 1920 Int8 MAC operation per cycle
- Support max192 Int16 MAC operation per cycle
- Support max 64 FP16 MAC operation per cycle
- 512KB internal buffer
- One isolated voltage domain to support DVFS
- Acuity models Github
System Memory
- RAM Memory Variants: 2GB DDR4.
- Storage Memory: SPI Flash and optional eMMC module from 16GB up to 128GB
SOEdge Baseboard Features
Network
- 10/100/1000Mbps Etherne
- WiFi 802.11 b/g/n with Bluetooth 4.0 (optional)
Storage
- microSD - bootable, support SDHC and SDXC, storage up to 256GB
- USB - 2 USB2.0 Host port
Expansion Ports
- DSI - Display Serial Interface, 4 lanes MiPi, up to 1080P
- CSI - CMOS Camera Interface up to 5 mega pixel
- TP - Touch Panel Port, SPI with interrupt
- RTC - Real Time Clock Battery Connector
- VBAT - Lithium Battery Connector with temperature sensor input
- Wifi/BT Module Header - SDIO 3.0 and UART
- 2x20 pins "Pi2" GPIO Header
- PCIe 2x open ended slot
SOEdge Module and Baseboard Information, Schematics, and Certifications
- Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
- Input Power: DC 12V @ 3A 5.5OD/2.1ID Barrel DC Jack connector
- SOEdge Module Schematic:
- SOEdge Module ver 2.0 20190919 Schematic
- SOEdge Module ver 2.0 20190919 PCB Component Placement Top PDF file
- SOEdge Module ver 2.0 20190919 PCB Component Placement Bottom PDF file
- SOEdge Module ver 2.0 20190919 PCB Component Placement Top Drawing file
- SOEdge Module ver 2.0 20190919 PCB Component Placement Bottom Drawing file
- SOEdge Module Pin Assignment ver 1.0 in Excel format(includes comparison chart to SOPine)
- SOEdge Module Pin Assignment ver 1.0 in Open Document format(includes comparison chart to SOPine)
- SOEdge Model "A" Baseboard Schematic and PCB Board Resource:
- SOEdge Neural AI Stick Schematic:
- SOEdge/SOPine/PINE A64 Wifi/BT module Schematic
- SOEdge module together with model "A" baseboard Certification:
- Disclaimer: Please note that SOEdge module is not a "final" product and in general certification is not necessary. However, SOEdge module still submits the mpdel A baseboard for FCC, CE, and ROHS certifications and obtain the certificates to prove that can pass the testing. Please note, a final commercial product needs to perform its own testing and obtain its own certificate.
- Not yet available
Datasheets for Components and Peripherals
- Rockchip RK1808 SoC information:
- Rockchip RK809 PMU (Power Management Unit) information:
- DDR4 information:
- eMMC information:
- SPI NOR Flash information:
- SOEdge Related:
- 5MPixel CMOS Camera module information:
- LCD Touch Screen Panel information:
- Ethernet PHY information:
- Wifi/BT module information:
- Enclosure information:
- Connector information:
SOEdge/SOPine Cluster Board Resource
- Cluster board is an hardware open source project and will be available at PINE64 store on late January 2018.
- Please note that this project is not "OSH" compliance.:
- Clusterboard version 2.2 Schematic Capture source file
- Clusterboard version 2.2 Schematic Capture PDF file
- Clusterboard version 2.2 PCB Job source file
- Clusterboard version 2.2 PCB Gerber file
- Clusterboard version 2.2 PCB Layout PDF file
- Clusterboard 20pins header definition
- Clusterboard 3D drawing in Fusion360
- Clusterboard PDF drawing
