Difference between revisions of "SOEDGE"

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* 512KB L2 cache
* 512KB L2 cache


=== GPU Architecture ===
* [http://www.arm.com/products/multimedia/mali-gpu/ultra-low-power/mali-400.php ARM Mali400MP2 Dual-core GPU]
* Support OpenGL ES 2.0 and OpenVG 1.1 standard


=== System Memory ===
=== System Memory ===
* RAM Memory Variants: 2GB LPDDR3.
* RAM Memory Variants: 2GB DDR4.
* Storage Memory: SPI Flash and optional eMMC module from 16GB up to 64GB
* Storage Memory: SPI Flash and optional eMMC module from 16GB up to 128GB


== PINE A64-LTS Board Features ==
== SOPine Baseboard Features ==


=== Video ===
=== Video ===
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=== Network ===
=== Network ===
* 10/100/1000Mbps Ethernet(PINE A64+ version), 10/100Mbps Ethernet(PINE A64 version)
* 10/100/1000Mbps Etherne
* WiFi 802.11 b/g/n with Bluetooth 4.0 (optional)
* WiFi 802.11 b/g/n with Bluetooth 4.0 (optional)


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* Wifi/BT Module Header - SDIO 3.0 and UART
* Wifi/BT Module Header - SDIO 3.0 and UART
* 2x20 pins "Pi2" GPIO Header
* 2x20 pins "Pi2" GPIO Header
* 2x17 pins "Euler" GPIO Header
* PCIe 2x open ended slot
* 2x5 pins "EXP" Console Header


== Pine A64-LTS, SOPine Module and Baseboard Information, Schematics, and Certifications ==
== SOEdge Module and Baseboard Information, Schematics, and Certifications ==
* Model "A" Baseoard Dimensions: 133mm x 80mm x 19mm
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 5V @ 2A, 3.7V Li-Ion battery connector, 3.5OD/1.35ID Barrel DC Jack connector, Euler connector
* Input Power: DC 5V @ 2A, 3.7V Li-Ion battery connector, 3.5OD/1.35ID Barrel DC Jack connector, Euler connector
* [http://wiki.pine64.org/images/7/7d/Pine64_Board_Connector.png PINE A64 Connector Layout @courtesy of norm24]
* [http://wiki.pine64.org/images/7/7d/Pine64_Board_Connector.png PINE A64 Connector Layout @courtesy of norm24]
* [http://wiki.pine64.org/images/d/da/Pine64_Connector.JPG PINE A64 Connector List]
* [http://wiki.pine64.org/images/d/da/Pine64_Connector.JPG PINE A64 Connector List]
* [http://files.pine64.org/doc/SOPINE-A64/SOPINE-A64-Pin-Assignments-ver-1.0.pdf SOPine Module Pin Assignment ver 1.0]
* [http://files.pine64.org/doc/SOEdge/SOEdge%20Pin%20Assignments%20ver%201.00.pdf SOEdge Module Pin Assignment ver 1.0(includes comparision chart to SOPine)]
* [https://forum.pine64.org/showthread.php?tid=8058 a PDF mapping the pins from the A64 chip itself, to the gold-fingers on the SO-DIMM edge, to the multiple connectors on the baseboard and on the clusterboard, attached to this forum post.]
* [https://forum.pine64.org/showthread.php?tid=8058 a PDF mapping the pins from the A64 chip itself, to the gold-fingers on the SO-DIMM edge, to the multiple connectors on the baseboard and on the clusterboard, attached to this forum post.]
* [http://files.pine64.org/doc/Pine%20A64%20Schematic/Pine%20A64%20Pin%20Assignment%20160119.pdf PINE A64 Pi-2/Eular/Ext Bus/Wifi Bus Connector Pin Assignment (Updated 15/Feb/2016)]
* [http://files.pine64.org/doc/Pine%20A64%20Schematic/Pine%20A64%20Pin%20Assignment%20160119.pdf PINE A64 Pi-2/Eular/Ext Bus/Wifi Bus Connector Pin Assignment (Updated 15/Feb/2016)]

Revision as of 23:14, 18 October 2020

Software and OS Image Downloads

SOEdge_Software_Release

penguin.png Armbian


Accessories Step-by-Step Guides

Under 'Guides for PINE64 model A accessories' you can find instructions and guides concerning:

  • Enclosures
  • Bluetooth and WiFi module
  • Real Time Clock (RTC) battery
  • Real Time Clock (RTC) battery holder
  • First and third party cases
  • Featured 3D printed cases (and more)

SoC and Memory Specification

  • Based on Rockchip RK1808
Allwinner A64.jpg

CPU Architecture

  • Quad-core ARM Cortex-A53 Processor@1152Mhz
  • A power-efficient ARM v8 architecture
  • 64 and 32bit execution states for scalable high performance
  • Support NEON Advanced SIMD (Single Instruction Multiple Data) instruction for acceleration of media and signal processing function
  • Support Large Physical Address Extensions(LPAE)
  • VFPv4 Floating Point Unit
  • 32KB L1 Instruction cache and 32KB L1 Data cache
  • 512KB L2 cache


System Memory

  • RAM Memory Variants: 2GB DDR4.
  • Storage Memory: SPI Flash and optional eMMC module from 16GB up to 128GB

SOPine Baseboard Features

Video

  • Digital Video (Type A - full)

Audio

  • 3.5mm stereo earphone/microphone plug

Network

  • 10/100/1000Mbps Etherne
  • WiFi 802.11 b/g/n with Bluetooth 4.0 (optional)

Storage

  • microSD - bootable, support SDHC and SDXC, storage up to 256GB
  • USB - 2 USB2.0 Host port

Expansion Ports

  • DSI - Display Serial Interface, 4 lanes MiPi, up to 1080P
  • CSI - CMOS Camera Interface up to 5 mega pixel
  • TP - Touch Panel Port, SPI with interrupt
  • RTC - Real Time Clock Battery Connector
  • VBAT - Lithium Battery Connector with temperature sensor input
  • Wifi/BT Module Header - SDIO 3.0 and UART
  • 2x20 pins "Pi2" GPIO Header
  • PCIe 2x open ended slot

SOEdge Module and Baseboard Information, Schematics, and Certifications

Datasheets for Components and Peripherals

SOEdge/SOPine Cluster Board Resource

Other Resources