Oz64

The Ox64

Powered by RISC-V

The Ox64 is a RISC-V based single-board computer based on the Bouffalo Lab BL808 RISC-V SoC with C906 64-bit and E907/E902 32-bit CPU cores supported by 64 MB of embedded PSRAM memory, and with built-in WiFi, Bluetooh and Zigbee radio interfaces. The Ox64 comes in a breadboard-friendly form-factor, has a microSD card slot, a USB 2.0 Type-C port, and many other peripheral interfaces for makers to integrate with sensors and other devices.

Software Releases

Quick Links to the Source of OS Images Build

There is a community effort to bring updated kernels, peripherals and buildroot - Lots of communication happening in the #oz64-nutcracker channel.

Toolchain:

• elf_newlib_toolchain/bin/riscv64-unknown-elf-gcc (Xuantie-900 elf newlib gcc Toolchain V2.2.5 B-20220323) 10.2.0
• linux_toolchain/bin/riscv64-unknown-linux-gnu-gcc (Xuantie-900 linux-5.10.4 glibc gcc Toolchain V2.2.4 B-20211227) 10.2.0
• cmake version 3.19.3

Software Development Kits

• SG200x NPU TDL SDK
• Fishwaldo SG200x Debian
• Lup Yuen Apache NuttX RTOS

SoC and Memory Specification

Based on the Sophgo SG-200x

CPU Architecture

T-Head C906 1GHz MHz 64-bit RISC-V CPU:

• Supports RISC-V RV64IMAFCV instruction architecture
• Five-stage single-issue sequentially executed pipeline
• Level-1 instruction and data cache of Harvard architecture, with a size of 32 KB and a cache line of 64KB
• Level-2 128KB cache
• Sv39 memory management unit, realizing the conversion of virtual and real addresses and memory management
• jTLB that supports 128 entries
• Supports AXI 4.0 128-bit master interface
• Supports core local interrupt (CLINT) and platform-level interrupt controller (PLIC)
• With 80 external interrupt sources, 3 bits for configuring interrupt priority
• Supports BHT (8K) and BTB
• Compatible with RISC-V PMP, 8 configurable areas
• Supports hardware performance monitor (HPM) units
• See here

T-Head C906 700Mhz MHz 64-bit RISC-V CPU:

• Supports RISC-V RV64IMAFCV instruction architecture
• Five-stage single-issue sequentially executed pipeline
• Level-1 instruction and data cache of Harvard architecture, with a size of 16 KB and a cache line of 16KB
• Sv39 memory management unit, realizing the conversion of virtual and real addresses and memory management
• jTLB that supports 128 entries
• Supports AXI 4.0 128-bit master interface
• Supports core local interrupt (CLINT) and platform-level interrupt controller (PLIC)
• With 80 external interrupt sources, 3 bits for configuring interrupt priority
• Supports BHT (8K) and BTB
• Compatible with RISC-V PMP, 8 configurable areas
• Supports hardware performance monitor (HPM) units
• See here

ARM Cortex-A53 1GHzz 64-bit RISC CPU:

• Quad-core Cortex-A53 up to 1.0GHz CPU
• Full implementation of the ARM architecture v8-A instruction set
• ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
• ARMv8 Cryptography Extensions
• In-order pipeline with symmetric dual-issue of most instructions
• Unified system L2 128KB cache
• Includes VFP v3 hardware to support single and double-precision operations
• Integrated 32KB L1 instruction cache, 32KB 4-way set associative L1 data cache
• TrustZone technology support
• PD_A53: Cortex-A53 + Neon + FPU + L1 I/D Cache of core 2/3

8051 25-300MHz 8-bit CPU:

• Integrated 8K SRAM

System Memory

• SIP DRAM 512MB

Board Features

Network

• 2.4 GHz 1T1R WiFi6
• Bluetooth 5.2
• 10/100 Mbit/s Ethernet with optional PoE capability

Storage

• On-board eMMC module socket
• MicroSD, supports SDHC and SDXC (only on the 128 Mbit version)

Expansion Ports

• USB 2.0 Host port
• 26 GPIO pins, including SPI, I²C and UART functionality
• Dual-lane MiPi CSI port
• Dual-lane MiPi DSI port

Board Information, Schematics and Certifications

Pinout for wiring ethernet PHY to EMAC

Board Dimensions: 85mm x 56mm x 18.8mm, see the model-B board dimension drawing

Input Power: +5V @2A with 3.5mm/1.35mm Type H Barrel type DC connector (@1A will work if there is no heavy load on the USB 2.0 port)

Pre-Production version schematic:

• Oz64 Schematic 20240517 v1.0.0
• Oz64 PCB Component placement(ToP) 20240517 v1.0.0
• Oz64 PCB Component placement(Bottom) 20240517 v1.0.0

Certifications:

• Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary.
• Not yet available

Datasheets for Components and Peripherals

Sophgo SG2000 SoC information:

• Sophgo SG2000 SoC Technical Reference Manual

Wifi/BT information:

• AIC Semi AIC8800DC Datasheet

Power Regulator information:

• Innovation Analog Tech IA2014 Step_down Converter Datasheet

MicroSD socket information:

• Push type microSD socket specification