Difference between revisions of "Ox64"

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** [https://files.pine64.org/doc/datasheet/ox64/IA2014-03.pdf Innovation Analog Tech IA2014 Step_down Converter Datasheet]
** [https://files.pine64.org/doc/datasheet/ox64/IA2014-03.pdf Innovation Analog Tech IA2014 Step_down Converter Datasheet]
* MicroSD socket information:
* MicroSD socket information:
** [https://files.pine64.org/doc/datasheet/ox64/TF%20PUSH%20type%20socket%20specification.pdf {ish type microSD socket specification]
** [https://files.pine64.org/doc/datasheet/ox64/TF%20PUSH%20type%20socket%20specification.pdf Push type microSD socket specification]


== Articles and Blogs ==
== Articles and Blogs ==

Revision as of 03:35, 6 December 2022

The Ox64

The Ox64 is a RISC-V based Single Board Computer powered by Bouffalo Lab BL808 C906 64-Bit RISC-V CPU, 32-Bit CPU, embedded 64MB PSRAM memory and build-on 3 radio RF (Wifi, BT, Zigbee). It provides breadboard friendly form factor, MicroSD Card slot, USB 2.0, and many other peripheral interfaces for makers to integrate with sensors and other devices.

RISC-V.png

Software Releases

Quick Links to the Source of OS Images Build

OS images are still in alpha build which are only fit for board bring up and testing purposes.

Software Development Kits


SoC and Memory Specification

Bouffalo Lab icon.png

BL808 Block Diagram.jpg


CPU Architecture

T-Head.png
    • Supports RISC-V RV64IMAFCV instruction architecture
    • Five-stage single-issue sequentially executed pipeline
    • Level-1 instruction and data cache of Harvard architecture, with a size of 32 KB and a cache line of 64B
    • Sv39 memory management unit, realizing the conversion of virtual and real addresses and memory management
    • jTLB that supports 128 entries
    • Supports AXI 4.0 128-bit master interface
    • Supports core local interrupt (CLINT) and platform-level interrupt controller (PLIC)
    • With 80 external interrupt sources, 3 bits for configuring interrupt priority
    • Supports BHT (8K) and BTB
    • Compatible with RISC-V PMP, 8 configurable areas
    • Supports hardware performance monitor (HPM) units
  • T_head E907 320MHz 32-bit RISC-V CPU
    • Supports RISC-V RV32IMAFCP instruction set
    • Supports RISC-V 32-bit/16-bit mixed instruction set
    • Supports RISC-V machine mode and user mode
    • Thirty-two 32-bit integer general purpose registers (GPR) and thirty-two 32-bit/64-bit floating-point GPRs
    • Integer (5-stage)/floating-point (7-stage), single-issue, sequentially executed pipeline
    • Supports AXI 4.0 main device interface and AHB 5.0 peripheral interface
    • 32K instruction cache, two-way set associative structure
    • 16K data cache, two-way set associative structure


System Memory

  • Embedded 64MB PSRAM

Board Features

Network

  • 2.4GHz 1T1R WiFi 802.11 b/g/n
  • Bluetooth 5.2
  • Zigbee
  • 10/100Mbps Ethernet (optional, on expansion board)

Storage

  • on-board 16Mb (2MB) or 128Mb (16MB) XSPI NOR flash memory
  • microSD - supports SDHC and SDXC

Expansion Ports

  • USB 2.0 OTG port
  • 26 GPIO Pins, including SPI, I2C and UART functionality. Possible I2S and GMII expansion
  • Dual lane MiPi CSI port, located at USB-C port, for camera module

Audio

  • mic (optional, on camera module)
  • speaker (optional, on camera module)


Board Information, Schematics and Certifications

  • Baseboard Dimensions: 51mm x 21mm x 19mm x 3.5mm (Breadboard friendly)
  • Input Power: 5V 0.5A microSD or USB-C port
  • Schematic:

Production version schematic:

Prototype (dispatched to developers) schematic:

  • Certifications:
    • Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary.
    • Not yet available

Datasheets for Components and Peripherals

Articles and Blogs

Development Efforts

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