CrystalGamma at 11:40, 31 December 2022

2022-12-31T11:40:08Z

← Older revision		Revision as of 11:40, 31 December 2022
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	* clock tree: while the register settings for muxes, dividers, and gates are described, which clock a gate or divider uses as input is not described. This makes understanding how to set the right frequency for a given piece of hardware difficult.		* clock tree: while the register settings for muxes, dividers, and gates are described, which clock a gate or divider uses as input is not described. This makes understanding how to set the right frequency for a given piece of hardware difficult.
	* DDR PHY: generally, I'm amazed at how good the documentation for the memory controller on the RK356x is. There are a couple of things where the register docs tell us to "Please reference to the chapter 9 to get more information" or similar (talking about the IP block's manual, which few people will have access to). For instance, what is the maximum VCO frequency of the PHY's PLL, and what is its reference clock (and which clock is used by the DDRC)?		* DDR PHY: generally, I'm amazed at how good the documentation for the memory controller on the RK356x is. There are a couple of things where the register docs tell us to "Please reference to the chapter 9 to get more information" or similar (talking about the IP block's manual, which few people will have access to). For instance, what is the maximum VCO frequency of the PHY's PLL, and what is its reference clock (and which clock is used by the DDRC)?
			* DDR scramble block: This seems like a very useful feature to have for security, but it's not documented, for either the RK356x or the RK3588.

CrystalGamma: Created page with "While I am glad that better register documentation for the RK356x's memory controller can be found (compared to the RK3399), there are a few important details missing from the RK3566 TRM. Docs that are not in any version of the RK356x TRM that I've seen, but are seemingly adequately covered by other TRMs: * OTP block: a similar (if not same) block is included in the PX3O, and covered in its TRM * PVTM/PVTPLL: RK3588 has docs for such blocks, but some signals (for insta..."

2022-12-31T11:25:26Z

Created page with "While I am glad that better register documentation for the RK356x's memory controller can be found (compared to the RK3399), there are a few important details missing from the RK3566 TRM. Docs that are not in any version of the RK356x TRM that I've seen, but are seemingly adequately covered by other TRMs: * OTP block: a similar (if not same) block is included in the PX3O, and covered in its TRM * PVTM/PVTPLL: RK3588 has docs for such blocks, but some signals (for insta..."

New page

While I am glad that better register documentation for the RK356x's memory controller can be found (compared to the RK3399), there are a few important details missing from the RK3566 TRM.

Docs that are not in any version of the RK356x TRM that I've seen, but are seemingly adequately covered by other TRMs:

* OTP block: a similar (if not same) block is included in the PX3O, and covered in its TRM
* PVTM/PVTPLL: RK3588 has docs for such blocks, but some signals (for instance 'bypass') don't seem to exist in the RK356x.

Hardware details specific to the RK356x that are not documented:

* (PMU_)SGRF: These are mostly TrustZone settings, they are essential for writing a secure monitor or boot firmware. I don't think there is anything gained by not publishing it (in fact transparency would make me much more confident in the security of the system).
* clock tree: while the register settings for muxes, dividers, and gates are described, which clock a gate or divider uses as input is not described. This makes understanding how to set the right frequency for a given piece of hardware difficult.
* DDR PHY: generally, I'm amazed at how good the documentation for the memory controller on the RK356x is. There are a couple of things where the register docs tell us to "Please reference to the chapter 9 to get more information" or similar (talking about the IP block's manual, which few people will have access to). For instance, what is the maximum VCO frequency of the PHY's PLL, and what is its reference clock (and which clock is used by the DDRC)?

User:CrystalGamma/RK3566 docs wishlist - Revision history

CrystalGamma at 11:40, 31 December 2022