Quartz64 - Revision history

Dsimic: /* Quartz64 Board Information, Schematics, and Certifications */ Wording improvements

2024-10-06T12:27:38Z

Quartz64 Board Information, Schematics, and Certifications: Wording improvements

← Older revision		Revision as of 12:27, 6 October 2024
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	=== Model "A" ===		=== Model "A" ===

	Model "A" ~~Baseboard Dimensions~~: 133mm x 80mm x 19mm		Model "A" dimensions: 133mm x 80mm x 19mm

	Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector		Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector
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	=== Model "B" ===		=== Model "B" ===

	Model "B" ~~Baseboard Dimensions~~: 85mm x 56mm x 18.8mm		Model "B" dimensions: 85mm x 56mm x 18.8mm

	Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID center-positive Barrel DC Jack connector		Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID center-positive Barrel DC Jack connector
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	=== Model "Zero" ===		=== Model "Zero" ===

	Model "Zero" ~~Baseboard Dimensions~~: 85mm x 56mm x 18.8mm		Model "Zero" dimensions: 85mm x 56mm x 18.8mm

	Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID center-positive Barrel DC Jack connector		Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID center-positive Barrel DC Jack connector

Dsimic: /* NPU (Neural Processing Unit) Capabilities */ Wording improvements

2024-10-06T12:26:52Z

NPU (Neural Processing Unit) Capabilities: Wording improvements

← Older revision		Revision as of 12:26, 6 October 2024
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	* Supports 38.4 GLOP/s when at 800MHz clock frequency		* Supports 38.4 GLOP/s when at 800MHz clock frequency

	=== NPU (Neural Processing Unit) Capabilities ~~(No NPU resent on model Zero)~~ ===		=== NPU (Neural Processing Unit) Capabilities ===

	* Neural network acceleration engine with processing performance of up to 0.8 TOPS		* Neural network acceleration engine with processing performance of up to 0.8 TOPS
	* Supports integer 8 and integer 16 convolution operations		* Supports integer 8 and integer 16 convolution operations
	* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet		* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

			Please note that no NPU is present on model "Zero".

	=== System Memory ===		=== System Memory ===

Dsimic: /* CPU Architecture */ Wording improvements

2024-10-06T12:25:14Z

CPU Architecture: Wording improvements

← Older revision		Revision as of 12:25, 6 October 2024
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	=== CPU Architecture ===		=== CPU Architecture ===

	* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.~~8GHz~~ (~~model Zero clock~~ up to 1.~~6Ghz~~)]		* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55] at 1.8 GHz (up to 1.6 GHz on model "Zero")
	* AArch32 for full backwards compatibility with ARMv7		* AArch32 for full backwards compatibility with ARMv7
	* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation		* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation

Tllim: /* Datasheets for Components and Peripherals */

2024-10-05T20:14:15Z

Datasheets for Components and Peripherals

← Older revision		Revision as of 20:14, 5 October 2024
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	== Datasheets for Components and Peripherals ==		== Datasheets for Components and Peripherals ==

	Rockchip RK3566 SoC information:		Rockchip RK3566 SoC information (model Zero using RK3566T which CPU speed clock at 1.6GHz and np NPU present):
	* [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]		* [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
	* [https://opensource.rock-chips.com/images/2/26/Rockchip_RK3568_TRM_Part1_V1.3-20220930P.PDF Rockchip RK3566 and RK3568 TRM (Technical Reference Manual)]		* [https://opensource.rock-chips.com/images/2/26/Rockchip_RK3568_TRM_Part1_V1.3-20220930P.PDF Rockchip RK3566 and RK3568 TRM (Technical Reference Manual)]

Tllim: /* SoC and Memory Specifications */

2024-10-05T20:08:49Z

SoC and Memory Specifications

← Older revision		Revision as of 20:08, 5 October 2024
Line 36:		Line 36:
	=== CPU Architecture ===		=== CPU Architecture ===

	* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]		* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz (model Zero clock up to 1.6Ghz)]
	* AArch32 for full backwards compatibility with ARMv7		* AArch32 for full backwards compatibility with ARMv7
	* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation		* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
Line 57:		Line 57:
	* Supports 38.4 GLOP/s when at 800MHz clock frequency		* Supports 38.4 GLOP/s when at 800MHz clock frequency

	=== NPU (Neural Processing Unit) Capabilities ===		=== NPU (Neural Processing Unit) Capabilities (No NPU resent on model Zero) ===

	* Neural network acceleration engine with processing performance of up to 0.8 TOPS		* Neural network acceleration engine with processing performance of up to 0.8 TOPS

Tllim: /* Datasheets for Components and Peripherals */

2024-09-18T19:41:18Z

Datasheets for Components and Peripherals

← Older revision		Revision as of 19:41, 18 September 2024
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	Wi-Fi/BT module info:		Wi-Fi/BT module info:
	* [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC Wi-Fi + Bluetooth5.0 Datasheet]		* [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC Wi-Fi + Bluetooth5.0 Datasheet for model "A" and "B"]
			* [https://files.pine64.org/doc/datasheet/quartz64/AIC8800DC%20Datasheet%20v1.0.pdf AICSemi AIC8800DC 11AX Wi-Fi + Bluetooth5.2 Datasheet for model "Zero"]

	IR LED:		IR LED:

Tllim: /* Quartz64 Board Information, Schematics, and Certifications */

2024-09-18T19:35:26Z

Quartz64 Board Information, Schematics, and Certifications

@@ Line 336: / Line 336: @@
 * Please note that v1.2 and V1.3 schematic and component placement are identical, just some component value changed.
 * Note: Model B uses a Molex PicoBlade compatible connector for the RTC battery. The Pine64 Backup Battery Holders come with a JST PH type connector. To use the Pine64 RTC Backup Battery Holder, the connector on the battery holder will need to be modified with a PicoBlade type connector.
 == Datasheets for Components and Peripherals ==

Dsimic: Oops, my bad

2023-11-14T07:56:33Z

Oops, my bad

← Older revision		Revision as of 07:56, 14 November 2023
Line 5:		Line 5:
	Key features include a PCIe x4 open-ended slot (model A) or M.2 slot (model B) using a single Gen2 lane electrically, and the use of LPDDR4 RAM.		Key features include a PCIe x4 open-ended slot (model A) or M.2 slot (model B) using a single Gen2 lane electrically, and the use of LPDDR4 RAM.

	The Quartz64 is available in two LPDDR4 system memory options: 4 GB and 8 GB. For booting, there is an eMMC module socket (supporting up to 128&~~mnsp~~;GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 Type-A host, 3x USB 2.0 host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I<sup>2</sup>C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.		The Quartz64 is available in two LPDDR4 system memory options: 4 GB and 8 GB. For booting, there is an eMMC module socket (supporting up to 128 GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 Type-A host, 3x USB 2.0 host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I<sup>2</sup>C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

	== Software releases ==		== Software releases ==

Dsimic: Small cleanups

2023-11-14T07:56:03Z

Small cleanups

← Older revision		Revision as of 07:56, 14 November 2023
Line 5:		Line 5:
	Key features include a PCIe x4 open-ended slot (model A) or M.2 slot (model B) using a single Gen2 lane electrically, and the use of LPDDR4 RAM.		Key features include a PCIe x4 open-ended slot (model A) or M.2 slot (model B) using a single Gen2 lane electrically, and the use of LPDDR4 RAM.

	The Quartz64 is available in two LPDDR4 system memory options: 4 GB and 8 GB. For booting, there is an eMMC module socket (supporting up to ~~128GB~~) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 ~~type~~ A ~~Host~~, 3x USB 2.0 ~~Host~~, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch ~~Panel~~ interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I<sup>2</sup>C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.		The Quartz64 is available in two LPDDR4 system memory options: 4 GB and 8 GB. For booting, there is an eMMC module socket (supporting up to 128&mnsp;GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 Type-A host, 3x USB 2.0 host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I<sup>2</sup>C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

	== Software releases ==		== Software releases ==

Dsimic: Undo revision 21135 by CameronNemo (talk) Actually, it isn't weird, values and units should be separated by spaces, and using non-brakable spaces ensures that they still go together after the text is wrapped

2023-11-14T07:54:55Z

Undo revision 21135 by CameronNemo (talk) Actually, it isn't weird, values and units should be separated by spaces, and using non-brakable spaces ensures that they still go together after the text is wrapped

← Older revision		Revision as of 07:54, 14 November 2023
Line 5:		Line 5:
	Key features include a PCIe x4 open-ended slot (model A) or M.2 slot (model B) using a single Gen2 lane electrically, and the use of LPDDR4 RAM.		Key features include a PCIe x4 open-ended slot (model A) or M.2 slot (model B) using a single Gen2 lane electrically, and the use of LPDDR4 RAM.

	The Quartz64 is available in two LPDDR4 system memory options: ~~4GB~~ and ~~8GB~~. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I<sup>2</sup>C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.		The Quartz64 is available in two LPDDR4 system memory options: 4 GB and 8 GB. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I<sup>2</sup>C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

	== Software releases ==		== Software releases ==