PINE64 - User contributions [en]

SOQuartz

2022-12-28T22:07:38Z

Microboars: /* SOQuartz Model-A Baseboard Features */

[[File:SOQuartz module-1s.jpg|400px|thumb|right|The SOQuartz]]

The '''SOQuartz''' is a RK3566 based compute module and parts of Quartz64 series.

== Software releases ==

The SOQuartz software releases can be found in the article [[SOQuartz Software Releases]].

== SoC and Memory Specification ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== Neural Process Unit NPU Capability ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB, 4GB, 8GB LPDDR4.
* Storage Memory: optional 128Mb SPI Flash and optional eMMC module from 16GB up to 128GB

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0

== SOQuartz exposed peripherals ==

=== Displays / Cameras ===

* 1x HDMI
* 2x DSI
* 1x eDP (Instead of HDMI1)
* 1x LVDS (not available when dual-mode DSI)
* 1x CSI 4-line

=== Connectivity ===

* 1x Ethernet (1Gbit)
* 1x USB 2.0 OTG
* 1x SD Card (SD)
* 1x PCIe 1-Line
* 28x GPIO (TBD)

== Connector Pins Definition ==
* [https://files.pine64.org/doc/quartz64/SOQuartz%20Connector%20Pin%20Assignments%20ver%201.0.ods SOQuartz Module Connector Pins Definition ver 1.0]

== SOQuartz Model-A Baseboard Features ==

[[File:SOQuartz_model-A_baseboard.jpg |400px|thumb|SOQuartz Model-A Baseboard]]
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5OD/2.1ID (IEC 60130-10 Type A) Barrel DC Jack connector

=== Storage ===
* microSD - bootable, support SDHC and SDXC, storage up to 2TB
* USB - 2 USB2.0 Host port

=== Expansion Ports ===
* MiPi-CSI - 1x 2 lanes, 1x 4 lanes
* MiPi-DSI - 1x 2 lanes, 1x 4 lanes
* 2x20 pins "Pi2" GPIO Header
* PCIe 1x open ended slot
* 1x5 pin USB Expansion Header (J15)

=== GPIO Pins ===

Attention! GPIOs are 3.3V!

Interesting alternate pin configurations are listed in [brackets].

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin no.
! scope="col" | Pin no.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 1
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| ''[I2C2_SDA_M1]'' GPIO4_B4_3V3 a
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| ''[I2C2_SCL_M1]'' GPIO4_B5_3V3 a
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| ''[GPCLK0]'' GPIO4_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| GPIO0_D1_3V3 ''[UART2_TX_M0]''
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| GPIO0_D0_3V3 ''[UART2_RX_M0]''
|-
| style="text-align:right;"| ''[I2S1_MCLK_M1]'' GPIO3_C6_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| GPIO3_C7_3V3 ''[I2S1_SCLK_M1]''
|-
| style="text-align:right;"| GPIO4_A0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO4_A2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GPIO4_A3_3V3
|-
| style="text-align:right;"| 3.3V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 17
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| GPIO4_A1_3V3
|-
| style="text-align:right;"| ''[SPI3_MOSI_M0]'' GPIO4_B2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| GND
|-
| style="text-align:right;"| ''[SPI3_MISO_M0]'' GPIO4_B0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 21
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 22
| style="text-align:left;"| GPIO4_B1_3V3
|-
| style="text-align:right;"| ''[SPI3_CLK_M0]'' GPIO4_B3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 23
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 24
| style="text-align:left;"| GPIO4_A6_3V3 ''[SPI3_CS0_M0]''
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 25
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 26
| style="text-align:left;"| GPIO4_A7_3V3 ''[SPI3_CS1_M0]''
|-
| style="text-align:right;"| ''[I2C3_SDA_M0]'' GPIO1_A0_3V3 a
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 27
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 28
| style="text-align:left;"| GPIO1_A1_3V3 ''[I2C3_SCL_M0]'' a
|-
| style="text-align:right;"| GPIO3_A5_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 29
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 30
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_D4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 31
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 32
| style="text-align:left;"| GPIO3_D6_3V3
|-
| style="text-align:right;"| GPIO3_D7_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 33
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 34
| style="text-align:left;"| GND
|-
| style="text-align:right;"| ''[I2S1_LRCK_M1]'' GPIO3_D0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 35
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 36
| style="text-align:left;"| GPIO3_D5_3V3
|-
| style="text-align:right;"| GPIO3_D3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 37
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 38
| style="text-align:left;"| GPIO3_D2_3V3 ''[I2S1_SDI_M1]''
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 39
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 40
| style="text-align:left;"| GPIO3_D1_3V3 ''[I2S1_SDO_M1]''
|}

====Notes====
<ol style="list-style-type:lower-alpha">
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
</ol>

Source: Page 11 of [https://files.pine64.org/doc/quartz64/SOQuartz-Model-A-Baseboard-Schematic-20220522.pdf the board schematics].
=== USB Expansion Header ===
{| class="wikitable plainrowheaders" border="1"
! scope="col" | Pin no
! scope="col" | Assigned To
|-
| style="text-align:left;"| 1
| style="text-align:center; | USB2_HOST_5V
|-
| style="text-align:left;"| 2
| style="text-align:center; | HOST_DM3
|-
| style="text-align:left;"| 3
| style="text-align:center; | HOST_DP3
|-
| style="text-align:left;"| 4
| style="text-align:center; | GND
|-
| style="text-align:left;"| 5
| style="text-align:center; | GND
|}

Source: Page 10 of [https://files.pine64.org/doc/quartz64/SOQuartz-Model-A-Baseboard-Schematic-20220522.pdf the board schematics].

== SOQuartz BLADE Baseboard Features ==

[[File:SOQuartz_BLADE_Dimension.jpg |400px|thumb|SOQuartz BLADE Baseboard]]
* SOQuartz BLADE Baseboard Dimensions: 200mm x 40mm x 15mm
* Input Power:
** DC 12V @ 3A 3.4OD/1.3ID (IEC 60130-10 Type E) Barrel DC Jack connector
** PoE

=== Storage ===
* microSD - bootable, support SDHC and SDXC, storage up to 2TB
* USB - USB2.0 Host port (with header for setting OTG ID pin)

=== Expansion Ports ===
* 2x20 pins "Pi2" GPIO Header
* M.2 slot
* PWM fan header

=== Jumpers ===
* OTG ID jumper
* GPIO voltage, select 3.3V or 1.8V
* PoE Enable

== SOQuartz Module and Baseboard Information, Schematics, and Certifications ==

* SOQuartz Module Schematic:
** [https://files.pine64.org/doc/quartz64/SOQuartz_SOM_schematic_v1.1_20210816.pdf SOQuartz Module ver 1.1 20210816 Schematic]
** [https://files.pine64.org/doc/quartz64/SOQuartz-PCB-placement-v1.1.pdf SOQuartz Module ver 1.1 20210816 PCB Component Placement]

* SOQuartz Model "A" Baseboard Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/SOQuartz-Model-A-Baseboard-Schematic-20220522.pdf SOQuartz Model-A baseboard 20220522 Schematic]
** [https://files.pine64.org/doc/quartz64/SOQuartz-Model-A-Baseboard-Component-Placement_top-20220522.pdf SOQuartz SOQuartz Model-A baseboard 20220522 PCB Top Component Placement]
** [https://files.pine64.org/doc/quartz64/SOQuartz_Model_A_Baseboard_Component_Placement_bottom_20220522.pdf SOQuartz SOQuartz Model-A baseboard 20220522 PCB Bottom Component Placement]

[[File:BLADE_1U_half_width_server_rack.jpg |400px|thumb|SOQuartz BLADE 3D Print 1U half width server rack]]
[[File:BLADE_1U_full_width_server_rack.jpg |400px|thumb|SOQuartz BLADE 3D Print 1U full width server rack]]
* SOQuartz Blade Baseboard Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/SOQuartz-BLADE-Baseboard-Schematic-20220522.pdf SOQuartz BLADE 20220522 Schematic]
** [https://files.pine64.org/doc/quartz64/SOQuartz-BLADE-PCB-Placement-20220522.pdf SOQuartz BLADE 20220522 PCB component Placement]
** [https://files.pine64.org/doc/quartz64/BLADE%201U%20Rack_3D.stp SOQuartz BLADE 1U Rack STP file]
[[File:BLADE_1U_rack_3D.jpg |400px]]

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for SOQuartz PMU]
* DDR4 information:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]
* i2C to PWM Controller user in BLADE info:
** [https://files.pine64.org/doc/datasheet/quartz64/GP7101_cn_V1_qsxn.pdf GP7101 i2c to PWM Controller Datasheet in Chinese]
** GP7101 i2c to PWM Controller Datasheet translated to English by neggles [[File:GP7101 cn V1 qsxn en.pdf]]
** I2C address is 0x58 despite what datasheet says
* PoE DC/DC Controller user in BLADE info:
** [https://files.pine64.org/doc/datasheet/quartz64/SD4954B%20Datasheet.pdf Silan SD4954B PD and DC/DC Controller compatible with IEEE 802.3AF standard Datasheet]

== SOQuartz Module with various CM4 carrier boards ==

* For CM4 carrier board comprehensive list, please visit [https://pipci.jeffgeerling.com/boards_cm Jeff Geerling collection]

[[File:SOQuartz_with_DF_Robot_carrier_board.jpg|400px|thumb|SOQuartz with DF Robot CM4 Carrier Board]]

[[File:SOQuartz_with_Waveshare_carrier_board.jpg|400px|thumb|SOQuartz with Waveshare CM4 Carrier Board]]

[[File:SOQuartz_with_Waveshare_PoE_carrier_board.jpg|400px|thumb|SOQuartz with Waveshare CM4 PoE Board]]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Other Resources ==

[[Category:SOQuartz]] [[Category:Quartz64]]

SOQuartz

2022-12-28T22:00:48Z

Microboars: /* Expansion Ports */

[[File:SOQuartz module-1s.jpg|400px|thumb|right|The SOQuartz]]

The '''SOQuartz''' is a RK3566 based compute module and parts of Quartz64 series.

== Software releases ==

The SOQuartz software releases can be found in the article [[SOQuartz Software Releases]].

== SoC and Memory Specification ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== Neural Process Unit NPU Capability ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB, 4GB, 8GB LPDDR4.
* Storage Memory: optional 128Mb SPI Flash and optional eMMC module from 16GB up to 128GB

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0

== SOQuartz exposed peripherals ==

=== Displays / Cameras ===

* 1x HDMI
* 2x DSI
* 1x eDP (Instead of HDMI1)
* 1x LVDS (not available when dual-mode DSI)
* 1x CSI 4-line

=== Connectivity ===

* 1x Ethernet (1Gbit)
* 1x USB 2.0 OTG
* 1x SD Card (SD)
* 1x PCIe 1-Line
* 28x GPIO (TBD)

== Connector Pins Definition ==
* [https://files.pine64.org/doc/quartz64/SOQuartz%20Connector%20Pin%20Assignments%20ver%201.0.ods SOQuartz Module Connector Pins Definition ver 1.0]

== SOQuartz Model-A Baseboard Features ==

[[File:SOQuartz_model-A_baseboard.jpg |400px|thumb|SOQuartz Model-A Baseboard]]
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5OD/2.1ID (IEC 60130-10 Type A) Barrel DC Jack connector

=== Storage ===
* microSD - bootable, support SDHC and SDXC, storage up to 2TB
* USB - 2 USB2.0 Host port

=== Expansion Ports ===
* MiPi-CSI - 1x 2 lanes, 1x 4 lanes
* MiPi-DSI - 1x 2 lanes, 1x 4 lanes
* 2x20 pins "Pi2" GPIO Header
* PCIe 1x open ended slot
* 1x5 pin USB Expansion Header (J15)

=== GPIO Pins ===

Attention! GPIOs are 3.3V!

Interesting alternate pin configurations are listed in [brackets].

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin no.
! scope="col" | Pin no.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 1
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| ''[I2C2_SDA_M1]'' GPIO4_B4_3V3 a
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| ''[I2C2_SCL_M1]'' GPIO4_B5_3V3 a
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| ''[GPCLK0]'' GPIO4_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| GPIO0_D1_3V3 ''[UART2_TX_M0]''
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| GPIO0_D0_3V3 ''[UART2_RX_M0]''
|-
| style="text-align:right;"| ''[I2S1_MCLK_M1]'' GPIO3_C6_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| GPIO3_C7_3V3 ''[I2S1_SCLK_M1]''
|-
| style="text-align:right;"| GPIO4_A0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO4_A2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GPIO4_A3_3V3
|-
| style="text-align:right;"| 3.3V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 17
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| GPIO4_A1_3V3
|-
| style="text-align:right;"| ''[SPI3_MOSI_M0]'' GPIO4_B2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| GND
|-
| style="text-align:right;"| ''[SPI3_MISO_M0]'' GPIO4_B0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 21
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 22
| style="text-align:left;"| GPIO4_B1_3V3
|-
| style="text-align:right;"| ''[SPI3_CLK_M0]'' GPIO4_B3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 23
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 24
| style="text-align:left;"| GPIO4_A6_3V3 ''[SPI3_CS0_M0]''
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 25
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 26
| style="text-align:left;"| GPIO4_A7_3V3 ''[SPI3_CS1_M0]''
|-
| style="text-align:right;"| ''[I2C3_SDA_M0]'' GPIO1_A0_3V3 a
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 27
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 28
| style="text-align:left;"| GPIO1_A1_3V3 ''[I2C3_SCL_M0]'' a
|-
| style="text-align:right;"| GPIO3_A5_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 29
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 30
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_D4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 31
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 32
| style="text-align:left;"| GPIO3_D6_3V3
|-
| style="text-align:right;"| GPIO3_D7_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 33
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 34
| style="text-align:left;"| GND
|-
| style="text-align:right;"| ''[I2S1_LRCK_M1]'' GPIO3_D0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 35
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 36
| style="text-align:left;"| GPIO3_D5_3V3
|-
| style="text-align:right;"| GPIO3_D3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 37
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 38
| style="text-align:left;"| GPIO3_D2_3V3 ''[I2S1_SDI_M1]''
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 39
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 40
| style="text-align:left;"| GPIO3_D1_3V3 ''[I2S1_SDO_M1]''
|}

===Notes===
<ol style="list-style-type:lower-alpha">
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
</ol>

Source: Page 11 of [https://files.pine64.org/doc/quartz64/SOQuartz-Model-A-Baseboard-Schematic-20220522.pdf the board schematics].

== SOQuartz BLADE Baseboard Features ==

[[File:SOQuartz_BLADE_Dimension.jpg |400px|thumb|SOQuartz BLADE Baseboard]]
* SOQuartz BLADE Baseboard Dimensions: 200mm x 40mm x 15mm
* Input Power:
** DC 12V @ 3A 3.4OD/1.3ID (IEC 60130-10 Type E) Barrel DC Jack connector
** PoE

=== Storage ===
* microSD - bootable, support SDHC and SDXC, storage up to 2TB
* USB - USB2.0 Host port (with header for setting OTG ID pin)

=== Expansion Ports ===
* 2x20 pins "Pi2" GPIO Header
* M.2 slot
* PWM fan header

=== Jumpers ===
* OTG ID jumper
* GPIO voltage, select 3.3V or 1.8V
* PoE Enable

== SOQuartz Module and Baseboard Information, Schematics, and Certifications ==

* SOQuartz Module Schematic:
** [https://files.pine64.org/doc/quartz64/SOQuartz_SOM_schematic_v1.1_20210816.pdf SOQuartz Module ver 1.1 20210816 Schematic]
** [https://files.pine64.org/doc/quartz64/SOQuartz-PCB-placement-v1.1.pdf SOQuartz Module ver 1.1 20210816 PCB Component Placement]

* SOQuartz Model "A" Baseboard Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/SOQuartz-Model-A-Baseboard-Schematic-20220522.pdf SOQuartz Model-A baseboard 20220522 Schematic]
** [https://files.pine64.org/doc/quartz64/SOQuartz-Model-A-Baseboard-Component-Placement_top-20220522.pdf SOQuartz SOQuartz Model-A baseboard 20220522 PCB Top Component Placement]
** [https://files.pine64.org/doc/quartz64/SOQuartz_Model_A_Baseboard_Component_Placement_bottom_20220522.pdf SOQuartz SOQuartz Model-A baseboard 20220522 PCB Bottom Component Placement]

[[File:BLADE_1U_half_width_server_rack.jpg |400px|thumb|SOQuartz BLADE 3D Print 1U half width server rack]]
[[File:BLADE_1U_full_width_server_rack.jpg |400px|thumb|SOQuartz BLADE 3D Print 1U full width server rack]]
* SOQuartz Blade Baseboard Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/SOQuartz-BLADE-Baseboard-Schematic-20220522.pdf SOQuartz BLADE 20220522 Schematic]
** [https://files.pine64.org/doc/quartz64/SOQuartz-BLADE-PCB-Placement-20220522.pdf SOQuartz BLADE 20220522 PCB component Placement]
** [https://files.pine64.org/doc/quartz64/BLADE%201U%20Rack_3D.stp SOQuartz BLADE 1U Rack STP file]
[[File:BLADE_1U_rack_3D.jpg |400px]]

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for SOQuartz PMU]
* DDR4 information:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]
* i2C to PWM Controller user in BLADE info:
** [https://files.pine64.org/doc/datasheet/quartz64/GP7101_cn_V1_qsxn.pdf GP7101 i2c to PWM Controller Datasheet in Chinese]
** GP7101 i2c to PWM Controller Datasheet translated to English by neggles [[File:GP7101 cn V1 qsxn en.pdf]]
** I2C address is 0x58 despite what datasheet says
* PoE DC/DC Controller user in BLADE info:
** [https://files.pine64.org/doc/datasheet/quartz64/SD4954B%20Datasheet.pdf Silan SD4954B PD and DC/DC Controller compatible with IEEE 802.3AF standard Datasheet]

== SOQuartz Module with various CM4 carrier boards ==

* For CM4 carrier board comprehensive list, please visit [https://pipci.jeffgeerling.com/boards_cm Jeff Geerling collection]

[[File:SOQuartz_with_DF_Robot_carrier_board.jpg|400px|thumb|SOQuartz with DF Robot CM4 Carrier Board]]

[[File:SOQuartz_with_Waveshare_carrier_board.jpg|400px|thumb|SOQuartz with Waveshare CM4 Carrier Board]]

[[File:SOQuartz_with_Waveshare_PoE_carrier_board.jpg|400px|thumb|SOQuartz with Waveshare CM4 PoE Board]]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Other Resources ==

[[Category:SOQuartz]] [[Category:Quartz64]]

SOQuartz

2022-12-28T21:56:25Z

Microboars: /* GPIO Pins */

[[File:SOQuartz module-1s.jpg|400px|thumb|right|The SOQuartz]]

The '''SOQuartz''' is a RK3566 based compute module and parts of Quartz64 series.

== Software releases ==

The SOQuartz software releases can be found in the article [[SOQuartz Software Releases]].

== SoC and Memory Specification ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== Neural Process Unit NPU Capability ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB, 4GB, 8GB LPDDR4.
* Storage Memory: optional 128Mb SPI Flash and optional eMMC module from 16GB up to 128GB

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0

== SOQuartz exposed peripherals ==

=== Displays / Cameras ===

* 1x HDMI
* 2x DSI
* 1x eDP (Instead of HDMI1)
* 1x LVDS (not available when dual-mode DSI)
* 1x CSI 4-line

=== Connectivity ===

* 1x Ethernet (1Gbit)
* 1x USB 2.0 OTG
* 1x SD Card (SD)
* 1x PCIe 1-Line
* 28x GPIO (TBD)

== Connector Pins Definition ==
* [https://files.pine64.org/doc/quartz64/SOQuartz%20Connector%20Pin%20Assignments%20ver%201.0.ods SOQuartz Module Connector Pins Definition ver 1.0]

== SOQuartz Model-A Baseboard Features ==

[[File:SOQuartz_model-A_baseboard.jpg |400px|thumb|SOQuartz Model-A Baseboard]]
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5OD/2.1ID (IEC 60130-10 Type A) Barrel DC Jack connector

=== Storage ===
* microSD - bootable, support SDHC and SDXC, storage up to 2TB
* USB - 2 USB2.0 Host port

=== Expansion Ports ===
* MiPi-CSI - 1x 2 lanes, 1x 4 lanes
* MiPi-DSI - 1x 2 lanes, 1x 4 lanes
* 2x20 pins "Pi2" GPIO Header
* PCIe 1x open ended slot

=== GPIO Pins ===

Attention! GPIOs are 3.3V!

Interesting alternate pin configurations are listed in [brackets].

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin no.
! scope="col" | Pin no.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 1
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| ''[I2C2_SDA_M1]'' GPIO4_B4_3V3 a
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| ''[I2C2_SCL_M1]'' GPIO4_B5_3V3 a
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| ''[GPCLK0]'' GPIO4_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| GPIO0_D1_3V3 ''[UART2_TX_M0]''
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| GPIO0_D0_3V3 ''[UART2_RX_M0]''
|-
| style="text-align:right;"| ''[I2S1_MCLK_M1]'' GPIO3_C6_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| GPIO3_C7_3V3 ''[I2S1_SCLK_M1]''
|-
| style="text-align:right;"| GPIO4_A0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO4_A2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GPIO4_A3_3V3
|-
| style="text-align:right;"| 3.3V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 17
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| GPIO4_A1_3V3
|-
| style="text-align:right;"| ''[SPI3_MOSI_M0]'' GPIO4_B2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| GND
|-
| style="text-align:right;"| ''[SPI3_MISO_M0]'' GPIO4_B0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 21
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 22
| style="text-align:left;"| GPIO4_B1_3V3
|-
| style="text-align:right;"| ''[SPI3_CLK_M0]'' GPIO4_B3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 23
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 24
| style="text-align:left;"| GPIO4_A6_3V3 ''[SPI3_CS0_M0]''
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 25
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 26
| style="text-align:left;"| GPIO4_A7_3V3 ''[SPI3_CS1_M0]''
|-
| style="text-align:right;"| ''[I2C3_SDA_M0]'' GPIO1_A0_3V3 a
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 27
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 28
| style="text-align:left;"| GPIO1_A1_3V3 ''[I2C3_SCL_M0]'' a
|-
| style="text-align:right;"| GPIO3_A5_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 29
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 30
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_D4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 31
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 32
| style="text-align:left;"| GPIO3_D6_3V3
|-
| style="text-align:right;"| GPIO3_D7_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 33
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 34
| style="text-align:left;"| GND
|-
| style="text-align:right;"| ''[I2S1_LRCK_M1]'' GPIO3_D0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 35
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 36
| style="text-align:left;"| GPIO3_D5_3V3
|-
| style="text-align:right;"| GPIO3_D3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 37
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 38
| style="text-align:left;"| GPIO3_D2_3V3 ''[I2S1_SDI_M1]''
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 39
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 40
| style="text-align:left;"| GPIO3_D1_3V3 ''[I2S1_SDO_M1]''
|}

===Notes===
<ol style="list-style-type:lower-alpha">
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
</ol>

Source: Page 11 of [https://files.pine64.org/doc/quartz64/SOQuartz-Model-A-Baseboard-Schematic-20220522.pdf the board schematics].

== SOQuartz BLADE Baseboard Features ==

[[File:SOQuartz_BLADE_Dimension.jpg |400px|thumb|SOQuartz BLADE Baseboard]]
* SOQuartz BLADE Baseboard Dimensions: 200mm x 40mm x 15mm
* Input Power:
** DC 12V @ 3A 3.4OD/1.3ID (IEC 60130-10 Type E) Barrel DC Jack connector
** PoE

=== Storage ===
* microSD - bootable, support SDHC and SDXC, storage up to 2TB
* USB - USB2.0 Host port (with header for setting OTG ID pin)

=== Expansion Ports ===
* 2x20 pins "Pi2" GPIO Header
* M.2 slot
* PWM fan header

=== Jumpers ===
* OTG ID jumper
* GPIO voltage, select 3.3V or 1.8V
* PoE Enable

== SOQuartz Module and Baseboard Information, Schematics, and Certifications ==

* SOQuartz Module Schematic:
** [https://files.pine64.org/doc/quartz64/SOQuartz_SOM_schematic_v1.1_20210816.pdf SOQuartz Module ver 1.1 20210816 Schematic]
** [https://files.pine64.org/doc/quartz64/SOQuartz-PCB-placement-v1.1.pdf SOQuartz Module ver 1.1 20210816 PCB Component Placement]

* SOQuartz Model "A" Baseboard Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/SOQuartz-Model-A-Baseboard-Schematic-20220522.pdf SOQuartz Model-A baseboard 20220522 Schematic]
** [https://files.pine64.org/doc/quartz64/SOQuartz-Model-A-Baseboard-Component-Placement_top-20220522.pdf SOQuartz SOQuartz Model-A baseboard 20220522 PCB Top Component Placement]
** [https://files.pine64.org/doc/quartz64/SOQuartz_Model_A_Baseboard_Component_Placement_bottom_20220522.pdf SOQuartz SOQuartz Model-A baseboard 20220522 PCB Bottom Component Placement]

[[File:BLADE_1U_half_width_server_rack.jpg |400px|thumb|SOQuartz BLADE 3D Print 1U half width server rack]]
[[File:BLADE_1U_full_width_server_rack.jpg |400px|thumb|SOQuartz BLADE 3D Print 1U full width server rack]]
* SOQuartz Blade Baseboard Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/SOQuartz-BLADE-Baseboard-Schematic-20220522.pdf SOQuartz BLADE 20220522 Schematic]
** [https://files.pine64.org/doc/quartz64/SOQuartz-BLADE-PCB-Placement-20220522.pdf SOQuartz BLADE 20220522 PCB component Placement]
** [https://files.pine64.org/doc/quartz64/BLADE%201U%20Rack_3D.stp SOQuartz BLADE 1U Rack STP file]
[[File:BLADE_1U_rack_3D.jpg |400px]]

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for SOQuartz PMU]
* DDR4 information:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]
* i2C to PWM Controller user in BLADE info:
** [https://files.pine64.org/doc/datasheet/quartz64/GP7101_cn_V1_qsxn.pdf GP7101 i2c to PWM Controller Datasheet in Chinese]
** GP7101 i2c to PWM Controller Datasheet translated to English by neggles [[File:GP7101 cn V1 qsxn en.pdf]]
** I2C address is 0x58 despite what datasheet says
* PoE DC/DC Controller user in BLADE info:
** [https://files.pine64.org/doc/datasheet/quartz64/SD4954B%20Datasheet.pdf Silan SD4954B PD and DC/DC Controller compatible with IEEE 802.3AF standard Datasheet]

== SOQuartz Module with various CM4 carrier boards ==

* For CM4 carrier board comprehensive list, please visit [https://pipci.jeffgeerling.com/boards_cm Jeff Geerling collection]

[[File:SOQuartz_with_DF_Robot_carrier_board.jpg|400px|thumb|SOQuartz with DF Robot CM4 Carrier Board]]

[[File:SOQuartz_with_Waveshare_carrier_board.jpg|400px|thumb|SOQuartz with Waveshare CM4 Carrier Board]]

[[File:SOQuartz_with_Waveshare_PoE_carrier_board.jpg|400px|thumb|SOQuartz with Waveshare CM4 PoE Board]]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Other Resources ==

[[Category:SOQuartz]] [[Category:Quartz64]]

SOQuartz

2022-12-28T21:27:33Z

Microboars: /* GPIO Pins */

[[File:SOQuartz module-1s.jpg|400px|thumb|right|The SOQuartz]]

The '''SOQuartz''' is a RK3566 based compute module and parts of Quartz64 series.

== Software releases ==

The SOQuartz software releases can be found in the article [[SOQuartz Software Releases]].

== SoC and Memory Specification ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== Neural Process Unit NPU Capability ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB, 4GB, 8GB LPDDR4.
* Storage Memory: optional 128Mb SPI Flash and optional eMMC module from 16GB up to 128GB

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0

== SOQuartz exposed peripherals ==

=== Displays / Cameras ===

* 1x HDMI
* 2x DSI
* 1x eDP (Instead of HDMI1)
* 1x LVDS (not available when dual-mode DSI)
* 1x CSI 4-line

=== Connectivity ===

* 1x Ethernet (1Gbit)
* 1x USB 2.0 OTG
* 1x SD Card (SD)
* 1x PCIe 1-Line
* 28x GPIO (TBD)

== Connector Pins Definition ==
* [https://files.pine64.org/doc/quartz64/SOQuartz%20Connector%20Pin%20Assignments%20ver%201.0.ods SOQuartz Module Connector Pins Definition ver 1.0]

== SOQuartz Model-A Baseboard Features ==

[[File:SOQuartz_model-A_baseboard.jpg |400px|thumb|SOQuartz Model-A Baseboard]]
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5OD/2.1ID (IEC 60130-10 Type A) Barrel DC Jack connector

=== Storage ===
* microSD - bootable, support SDHC and SDXC, storage up to 2TB
* USB - 2 USB2.0 Host port

=== Expansion Ports ===
* MiPi-CSI - 1x 2 lanes, 1x 4 lanes
* MiPi-DSI - 1x 2 lanes, 1x 4 lanes
* 2x20 pins "Pi2" GPIO Header
* PCIe 1x open ended slot

=== GPIO Pins ===

Attention! GPIOs are 3.3V!

Interesting alternate pin configurations are listed in [brackets].

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin no.
! scope="col" | Pin no.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 1
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| ''[I2C2_SDA_M1]'' GPIO4_B4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| ''[I2C2_SCL_M1]'' GPIO4_B5_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| ''[GPCLK0]'' GPIO4_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| GPIO0_D1_3V3 ''[UART2_TX_M0]''
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| GPIO0_D0_3V3 ''[UART2_RX_M0]''
|-
| style="text-align:right;"| ''[I2S1_MCLK_M1]'' GPIO3_C6_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| GPIO3_C7_3V3 ''[I2S1_SCLK_M1]''
|-
| style="text-align:right;"| GPIO4_A0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO4_A2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GPIO4_A3_3V3
|-
| style="text-align:right;"| 3.3V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 17
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| GPIO4_A1_3V3
|-
| style="text-align:right;"| ''[SPI3_MOSI_M0]'' GPIO4_B2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| GND
|-
| style="text-align:right;"| ''[SPI3_MISO_M0]'' GPIO4_B0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 21
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 22
| style="text-align:left;"| GPIO4_B1_3V3
|-
| style="text-align:right;"| ''[SPI3_CLK_M0]'' GPIO4_B3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 23
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 24
| style="text-align:left;"| GPIO4_A6_3V3 ''[SPI3_CS0_M0]''
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 25
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 26
| style="text-align:left;"| GPIO4_A7_3V3 ''[SPI3_CS1_M0]''
|-
| style="text-align:right;"| ''[I2C3_SDA_M0]'' GPIO1_A0_3V3
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 27
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 28
| style="text-align:left;"| GPIO1_A1_3V3 ''[I2C3_SCL_M0]''
|-
| style="text-align:right;"| GPIO3_A5_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 29
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 30
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_D4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 31
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 32
| style="text-align:left;"| GPIO3_D6_3V3
|-
| style="text-align:right;"| GPIO3_D7_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 33
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 34
| style="text-align:left;"| GND
|-
| style="text-align:right;"| ''[I2S1_LRCK_M1]'' GPIO3_D0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 35
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 36
| style="text-align:left;"| GPIO3_D5_3V3
|-
| style="text-align:right;"| GPIO3_D3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 37
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 38
| style="text-align:left;"| GPIO3_D2_3V3 ''[I2S1_SDI_M1]''
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 39
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 40
| style="text-align:left;"| GPIO3_D1_3V3 ''[I2S1_SDO_M1]''
|}

Source: Page 11 of [https://files.pine64.org/doc/quartz64/SOQuartz-Model-A-Baseboard-Schematic-20220522.pdf the board schematics].

== SOQuartz BLADE Baseboard Features ==

[[File:SOQuartz_BLADE_Dimension.jpg |400px|thumb|SOQuartz BLADE Baseboard]]
* SOQuartz BLADE Baseboard Dimensions: 200mm x 40mm x 15mm
* Input Power:
** DC 12V @ 3A 3.4OD/1.3ID (IEC 60130-10 Type E) Barrel DC Jack connector
** PoE

=== Storage ===
* microSD - bootable, support SDHC and SDXC, storage up to 2TB
* USB - USB2.0 Host port (with header for setting OTG ID pin)

=== Expansion Ports ===
* 2x20 pins "Pi2" GPIO Header
* M.2 slot
* PWM fan header

=== Jumpers ===
* OTG ID jumper
* GPIO voltage, select 3.3V or 1.8V
* PoE Enable

== SOQuartz Module and Baseboard Information, Schematics, and Certifications ==

* SOQuartz Module Schematic:
** [https://files.pine64.org/doc/quartz64/SOQuartz_SOM_schematic_v1.1_20210816.pdf SOQuartz Module ver 1.1 20210816 Schematic]
** [https://files.pine64.org/doc/quartz64/SOQuartz-PCB-placement-v1.1.pdf SOQuartz Module ver 1.1 20210816 PCB Component Placement]

* SOQuartz Model "A" Baseboard Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/SOQuartz-Model-A-Baseboard-Schematic-20220522.pdf SOQuartz Model-A baseboard 20220522 Schematic]
** [https://files.pine64.org/doc/quartz64/SOQuartz-Model-A-Baseboard-Component-Placement_top-20220522.pdf SOQuartz SOQuartz Model-A baseboard 20220522 PCB Top Component Placement]
** [https://files.pine64.org/doc/quartz64/SOQuartz_Model_A_Baseboard_Component_Placement_bottom_20220522.pdf SOQuartz SOQuartz Model-A baseboard 20220522 PCB Bottom Component Placement]

[[File:BLADE_1U_half_width_server_rack.jpg |400px|thumb|SOQuartz BLADE 3D Print 1U half width server rack]]
[[File:BLADE_1U_full_width_server_rack.jpg |400px|thumb|SOQuartz BLADE 3D Print 1U full width server rack]]
* SOQuartz Blade Baseboard Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/SOQuartz-BLADE-Baseboard-Schematic-20220522.pdf SOQuartz BLADE 20220522 Schematic]
** [https://files.pine64.org/doc/quartz64/SOQuartz-BLADE-PCB-Placement-20220522.pdf SOQuartz BLADE 20220522 PCB component Placement]
** [https://files.pine64.org/doc/quartz64/BLADE%201U%20Rack_3D.stp SOQuartz BLADE 1U Rack STP file]
[[File:BLADE_1U_rack_3D.jpg |400px]]

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for SOQuartz PMU]
* DDR4 information:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]
* i2C to PWM Controller user in BLADE info:
** [https://files.pine64.org/doc/datasheet/quartz64/GP7101_cn_V1_qsxn.pdf GP7101 i2c to PWM Controller Datasheet in Chinese]
** GP7101 i2c to PWM Controller Datasheet translated to English by neggles [[File:GP7101 cn V1 qsxn en.pdf]]
** I2C address is 0x58 despite what datasheet says
* PoE DC/DC Controller user in BLADE info:
** [https://files.pine64.org/doc/datasheet/quartz64/SD4954B%20Datasheet.pdf Silan SD4954B PD and DC/DC Controller compatible with IEEE 802.3AF standard Datasheet]

== SOQuartz Module with various CM4 carrier boards ==

* For CM4 carrier board comprehensive list, please visit [https://pipci.jeffgeerling.com/boards_cm Jeff Geerling collection]

[[File:SOQuartz_with_DF_Robot_carrier_board.jpg|400px|thumb|SOQuartz with DF Robot CM4 Carrier Board]]

[[File:SOQuartz_with_Waveshare_carrier_board.jpg|400px|thumb|SOQuartz with Waveshare CM4 Carrier Board]]

[[File:SOQuartz_with_Waveshare_PoE_carrier_board.jpg|400px|thumb|SOQuartz with Waveshare CM4 PoE Board]]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Other Resources ==

[[Category:SOQuartz]] [[Category:Quartz64]]

SOQuartz

2022-12-28T21:26:42Z

Microboars: /* SOQuartz Model-A Baseboard Features */

[[File:SOQuartz module-1s.jpg|400px|thumb|right|The SOQuartz]]

The '''SOQuartz''' is a RK3566 based compute module and parts of Quartz64 series.

== Software releases ==

The SOQuartz software releases can be found in the article [[SOQuartz Software Releases]].

== SoC and Memory Specification ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== Neural Process Unit NPU Capability ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB, 4GB, 8GB LPDDR4.
* Storage Memory: optional 128Mb SPI Flash and optional eMMC module from 16GB up to 128GB

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0

== SOQuartz exposed peripherals ==

=== Displays / Cameras ===

* 1x HDMI
* 2x DSI
* 1x eDP (Instead of HDMI1)
* 1x LVDS (not available when dual-mode DSI)
* 1x CSI 4-line

=== Connectivity ===

* 1x Ethernet (1Gbit)
* 1x USB 2.0 OTG
* 1x SD Card (SD)
* 1x PCIe 1-Line
* 28x GPIO (TBD)

== Connector Pins Definition ==
* [https://files.pine64.org/doc/quartz64/SOQuartz%20Connector%20Pin%20Assignments%20ver%201.0.ods SOQuartz Module Connector Pins Definition ver 1.0]

== SOQuartz Model-A Baseboard Features ==

[[File:SOQuartz_model-A_baseboard.jpg |400px|thumb|SOQuartz Model-A Baseboard]]
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5OD/2.1ID (IEC 60130-10 Type A) Barrel DC Jack connector

=== Storage ===
* microSD - bootable, support SDHC and SDXC, storage up to 2TB
* USB - 2 USB2.0 Host port

=== Expansion Ports ===
* MiPi-CSI - 1x 2 lanes, 1x 4 lanes
* MiPi-DSI - 1x 2 lanes, 1x 4 lanes
* 2x20 pins "Pi2" GPIO Header
* PCIe 1x open ended slot

=== GPIO Pins ===

Attention! GPIOs are 3.3V!

Interesting alternate pin configurations are listed in [brackets].

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin no.
! scope="col" | Pin no.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 1
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| ''[I2C2_SDA_M1]'' GPIO4_B4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| ''[I2C2_SCL_M1]'' GPIO4_B5_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| ''[GPCLK0]'' GPIO4_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX GPIO0_D1_3V3 ''[UART2_TX_M0]''
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX GPIO0_D0_3V3 ''[UART2_RX_M0]''
|-
| style="text-align:right;"| ''[I2S1_MCLK_M1]'' GPIO3_C6_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| GPIO3_C7_3V3 ''[I2S1_SCLK_M1]''
|-
| style="text-align:right;"| GPIO4_A0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO4_A2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GPIO4_A3_3V3
|-
| style="text-align:right;"| 3.3V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 17
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| GPIO4_A1_3V3
|-
| style="text-align:right;"| ''[SPI3_MOSI_M0]'' GPIO4_B2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| GND
|-
| style="text-align:right;"| ''[SPI3_MISO_M0]'' GPIO4_B0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 21
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 22
| style="text-align:left;"| GPIO4_B1_3V3
|-
| style="text-align:right;"| ''[SPI3_CLK_M0]'' GPIO4_B3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 23
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 24
| style="text-align:left;"| GPIO4_A6_3V3 ''[SPI3_CS0_M0]''
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 25
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 26
| style="text-align:left;"| GPIO4_A7_3V3 ''[SPI3_CS1_M0]''
|-
| style="text-align:right;"| ''[I2C3_SDA_M0]'' GPIO1_A0_3V3
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 27
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 28
| style="text-align:left;"| GPIO1_A1_3V3 ''[I2C3_SCL_M0]''
|-
| style="text-align:right;"| GPIO3_A5_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 29
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 30
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_D4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 31
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 32
| style="text-align:left;"| GPIO3_D6_3V3
|-
| style="text-align:right;"| GPIO3_D7_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 33
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 34
| style="text-align:left;"| GND
|-
| style="text-align:right;"| ''[I2S1_LRCK_M1]'' GPIO3_D0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 35
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 36
| style="text-align:left;"| GPIO3_D5_3V3
|-
| style="text-align:right;"| GPIO3_D3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 37
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 38
| style="text-align:left;"| GPIO3_D2_3V3 ''[I2S1_SDI_M1]''
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 39
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 40
| style="text-align:left;"| GPIO3_D1_3V3 ''[I2S1_SDO_M1]''
|}

Source: Page 11 of [https://files.pine64.org/doc/quartz64/SOQuartz-Model-A-Baseboard-Schematic-20220522.pdf the board schematics].

== SOQuartz BLADE Baseboard Features ==

[[File:SOQuartz_BLADE_Dimension.jpg |400px|thumb|SOQuartz BLADE Baseboard]]
* SOQuartz BLADE Baseboard Dimensions: 200mm x 40mm x 15mm
* Input Power:
** DC 12V @ 3A 3.4OD/1.3ID (IEC 60130-10 Type E) Barrel DC Jack connector
** PoE

=== Storage ===
* microSD - bootable, support SDHC and SDXC, storage up to 2TB
* USB - USB2.0 Host port (with header for setting OTG ID pin)

=== Expansion Ports ===
* 2x20 pins "Pi2" GPIO Header
* M.2 slot
* PWM fan header

=== Jumpers ===
* OTG ID jumper
* GPIO voltage, select 3.3V or 1.8V
* PoE Enable

== SOQuartz Module and Baseboard Information, Schematics, and Certifications ==

* SOQuartz Module Schematic:
** [https://files.pine64.org/doc/quartz64/SOQuartz_SOM_schematic_v1.1_20210816.pdf SOQuartz Module ver 1.1 20210816 Schematic]
** [https://files.pine64.org/doc/quartz64/SOQuartz-PCB-placement-v1.1.pdf SOQuartz Module ver 1.1 20210816 PCB Component Placement]

* SOQuartz Model "A" Baseboard Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/SOQuartz-Model-A-Baseboard-Schematic-20220522.pdf SOQuartz Model-A baseboard 20220522 Schematic]
** [https://files.pine64.org/doc/quartz64/SOQuartz-Model-A-Baseboard-Component-Placement_top-20220522.pdf SOQuartz SOQuartz Model-A baseboard 20220522 PCB Top Component Placement]
** [https://files.pine64.org/doc/quartz64/SOQuartz_Model_A_Baseboard_Component_Placement_bottom_20220522.pdf SOQuartz SOQuartz Model-A baseboard 20220522 PCB Bottom Component Placement]

[[File:BLADE_1U_half_width_server_rack.jpg |400px|thumb|SOQuartz BLADE 3D Print 1U half width server rack]]
[[File:BLADE_1U_full_width_server_rack.jpg |400px|thumb|SOQuartz BLADE 3D Print 1U full width server rack]]
* SOQuartz Blade Baseboard Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/SOQuartz-BLADE-Baseboard-Schematic-20220522.pdf SOQuartz BLADE 20220522 Schematic]
** [https://files.pine64.org/doc/quartz64/SOQuartz-BLADE-PCB-Placement-20220522.pdf SOQuartz BLADE 20220522 PCB component Placement]
** [https://files.pine64.org/doc/quartz64/BLADE%201U%20Rack_3D.stp SOQuartz BLADE 1U Rack STP file]
[[File:BLADE_1U_rack_3D.jpg |400px]]

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for SOQuartz PMU]
* DDR4 information:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]
* i2C to PWM Controller user in BLADE info:
** [https://files.pine64.org/doc/datasheet/quartz64/GP7101_cn_V1_qsxn.pdf GP7101 i2c to PWM Controller Datasheet in Chinese]
** GP7101 i2c to PWM Controller Datasheet translated to English by neggles [[File:GP7101 cn V1 qsxn en.pdf]]
** I2C address is 0x58 despite what datasheet says
* PoE DC/DC Controller user in BLADE info:
** [https://files.pine64.org/doc/datasheet/quartz64/SD4954B%20Datasheet.pdf Silan SD4954B PD and DC/DC Controller compatible with IEEE 802.3AF standard Datasheet]

== SOQuartz Module with various CM4 carrier boards ==

* For CM4 carrier board comprehensive list, please visit [https://pipci.jeffgeerling.com/boards_cm Jeff Geerling collection]

[[File:SOQuartz_with_DF_Robot_carrier_board.jpg|400px|thumb|SOQuartz with DF Robot CM4 Carrier Board]]

[[File:SOQuartz_with_Waveshare_carrier_board.jpg|400px|thumb|SOQuartz with Waveshare CM4 Carrier Board]]

[[File:SOQuartz_with_Waveshare_PoE_carrier_board.jpg|400px|thumb|SOQuartz with Waveshare CM4 PoE Board]]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Other Resources ==

[[Category:SOQuartz]] [[Category:Quartz64]]