PINE64 - User contributions [en]

Quartz64

2022-09-27T01:33:30Z

Davelong: added datasheet for IR led

[[File:Quartz64modelb.png|400px|thumb|right|The Quartz64 Model B]]

The '''Quartz64''' is the most recent Single Board Computer offering from PINE64, with Model A initially released in June of 2021 and Model B in May of 2022. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software releases ==

{{warning|Software for the Quartz64 is still early in development, and therefore currently lacks features such as the ability to produce video output. You are strongly encouraged to procure a 3.3V UART serial adapter capable of running at 1.5 mbauds, such as [https://pine64.com/product/serial-console-woodpecker-edition/ the woodpecker] if you want to use a Quartz64 at this stage.}}
{{note|'''Note:''' OS images are provided by the community, not by PINE64. Most community projects currently aim at getting mainline Linux running on the board, not some vendor provided kernel that will never be receiving updates. A mainline-first approach allows for the boards to continue receiving important updates, such as security updates, for years to come, as well as have higher quality code in the kernel as it underwent independent review, but does mean that not all aspects of the hardware work right out of the gate.}}

=== Armbian ===
[[File:armbian.png|right|100px]]

Armbian is a base operating system platform for single board computers

* Lightweight Debian or Ubuntu based Linux distribution specialised for ARM development boards
* Each system is compiled, assembled and optimised by [https://github.com/armbian/build Armbian Build Tools]
* It has powerful build and software development tools to make custom builds

Download [https://github.com/armbian/build/releases/ latest, as fresh as possible, upon code change, images]

Support on Armbian forums https://forum.armbian.com/forum/96-upcoming-hardware-wip/

=== Manjaro ARM ===
[[File:Manjaro.png|right|100px]]

Manjaro ARM is a user friendly rolling release distribution, based on Arch Linux ARM.

* [https://github.com/manjaro-arm/quartz64-a-images/releases Images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

Most of the hardware support is already available in the mainline kernel. If some devices doesn't work it is possible to swap to the linux-quartz64 kernel <code>pacman -S linux-quartz64</code>.

Following desktop options available:
* Gnome
* KDE Plasma
* Mate
* Sway
* XFCE
as well as minimal image without desktop.

=== pgwipeout's Quartz64 CI ===

pgwipeout provides continuously rebuilt set of images for Quartz64 devices which includes a Debian installer and a buildroot rescue environment. It is aimed at advanced users who generally know their way around a Linux system, and as a baseline for whether something is working or not. Works on both SD cards and eMMC, uses pgwipeout's patched kernel. Kernels aren't auto-updated on the installed system, so the user manually has to do this by mounting the actual correct boot partition.

'''Download:''' https://gitlab.com/pgwipeout/quartz64_ci/-/pipelines (Click the three dots on the right, download the merge-job archive.)

For Quartz64 Model A, flash <tt>rk3566-quartz64-a.dtb.img.xz</tt>. On Linux, you can for example do this as follows, assuming your target device is <tt>/dev/sdX</tt>:

sudo -i; xzcat /path/to/rk3566-quartz64-a.dtb.img.xz > /dev/sdX

For Quartz64 Model B, use <tt>rk3566-quartz64-b.dtb.img.xz</tt> instead.

For line by line instructions to boot Quartz64 CI on a microSD card and use it to install Debian onto an eMMC follow these instructions https://wiki.pine64.org/wiki/Installing_Debian_on_the_Quartz64

=== Arch Linux ARM (Unofficial) ===

See [[Installing Arch Linux ARM On The Quartz64]] for detailed instructions.

=== Tianocore EDK II port by jmcneill ===

This (as of 2021-12-30) is a work in progress to enable UEFI enabled systems, and is able to bring up SD, eMMC, USB, PCIe with SATA and NVMe, HDMI, thermal sensors, TRNG, as well as general Cortex A-55 features. Known to work with NetBSD -current, and the ESXi Arm fling version 1.8.

* [https://github.com/jaredmcneill/quartz64_uefi jmcneill's Quartz64 UEFI Github]

The sdcard image should be written to an microSD card and installed. Currently, using this card also for the OS may be problematic.

=== NetBSD ===

NetBSD relies upon the UEFI support in Tianocore. Before NetBSD 10 is released, the latest version of NetBSD-current should be used:

* [http://nycdn.netbsd.org/pub/NetBSD-daily/HEAD/ NetBSD daily builds top level] from inside here, navigate to a date, and inside the images/ subdirectory are installable images. Use the one called "NetBSD-<version>-evbarm-aarch64-install.img.gz". This image can be written to a supported device, such as the eMMC interface, any USB storage device, NVMe, and PCIe AHCI SATA are all supported with builds after 2022-01-15.

* Currently this can not be shared with the EDK2 port, ie, microSD for EDK2 and some other media for NetBSD.

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support
* [https://www.cnx-software.com/2020/12/01/rockchip-rk3568-processor-to-power-edge-computing-and-nvr-applications 22nm process, believed to be FD-SOI]

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB (SOQuartz only), 4GB, 8GB LPDDR4.

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB
** Model A: 2 USB 2.0 host ports, 1 USB 2.0 OTG port, 1 USB 3.0 host port
** Model B: 1 USB 2.0 host port, 1 USB 2.0 OTG port, 1 USB 3.0 host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 8GB up to 128GB
* 64 Mbit (8 MByte) SPI flash (Model B only), part number <tt>25Q64DWZPIG</tt> in the schematic

==== eMMC Speeds ====

On a 64 GB eMMC module:

$ sudo hdparm -tT /dev/mmcblk1

/dev/mmcblk1:
Timing cached reads: 2368 MB in 2.00 seconds = 1184.46 MB/sec
Timing buffered disk reads: 452 MB in 3.01 seconds = 149.98 MB/sec

=== Expansion Ports ===
* HDMI
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints
** On Model A, the slot provides 10W of power for the 3.3V supply and however much power your 12V input power supply provides on the 12V supply

The PCIe implementation on the RK3566 is much more compatible with a wide range of devices compared to the one on the RK3399 used on the ROCKPro64. This means a lot more devices should work (excluding dGPUs due to a lack of cache snooping ability).

==== Combo PHYs ====

[[File:rk3566 phy.png]]

Several of the I/O options on the RK3566 used in the Quartz64 are using the same I/O lines, meaning that they cannot be used at the same time. The above diagram illustrates how they are connected.

In particular, USB 3.0 and the SATA connector on the board are mutually exclusive, and the PCI-e 2.0 lane can be reconfigured into a second SATA port, though an adapter cable needs to be fashioned for this to be useful.

=== GPIO Pins (Quartz64 Model A) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin no.
! scope="col" | Pin no.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX a
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX a
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT c
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

====Notes====
<ol style="list-style-type:lower-alpha">
<li>can be a PWM pin</li>
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
<li>low-pass filtered with cutoff of 220 MHz</li>
</ol>

Source: Page 28 of [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf the board schematics].

=== GPIO Pins (Quartz64 Model B) ===

Attention! GPIOs are 3.3V!

Interesting alternate pin configurations are listed in [brackets].

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin no.
! scope="col" | Pin no.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 1
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| ''[I2C3_SDA_M0]'' GPIO1_A0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| ''[I2C3_SCL_M0]'' GPIO1_A1_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_C4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX
|-
| style="text-align:right;"| ''[SPI1_CS0_M1]'' GPIO3_A1_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| GPIO3_A3_3V3
|-
| style="text-align:right;"| GPIO3_A2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GPIO3_B1_3V3
|-
| style="text-align:right;"| 3.3V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 17
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| GPIO3_B2_3V3
|-
| style="text-align:right;"| GPIO4_C3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO4_C5_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 21
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 22
| style="text-align:left;"| GPIO3_C1_3V3 ''[SPI1_MOSI_M1]''
|-
| style="text-align:right;"| GPIO4_C2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 23
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 24
| style="text-align:left;"| GPIO4_C6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 25
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 26
| style="text-align:left;"| GPIO4_D1_3V3
|-
| style="text-align:right;"| I2C4_SDA_M0
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 27
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 28
| style="text-align:left;"| I2C4_SCL_M0
|-
| style="text-align:right;"| GPIO3_B3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 29
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 30
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 31
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 32
| style="text-align:left;"| GPIO3_C2_3V3 ''[SPI1_MISO_M1]''
|-
| style="text-align:right;"| ''[SPI1_CLK_M1]'' GPIO3_C3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 33
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 34
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 35
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 36
| style="text-align:left;"| GPIO3_A7_3V3
|-
| style="text-align:right;"| ''[SPDIF_TX_M0]'' GPIO1_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 37
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 38
| style="text-align:left;"| GPIO3_A6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 39
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 40
| style="text-align:left;"| GPIO3_A5_3V3
|}

Source: Page 24 of [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf the board schematics].

== Quartz64 Board Information, Schematics, and Certifications ==

=== Model "A" ===
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Quartz64 Model "A" SBC Schematic ver 2.0 20210427 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V2.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Certifications:
** Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary. However, PINE64 still submit the SBC for FCC and CE certification and obtain the certificates to proof that SBC board is capable on passing the testing. Please note a final commercial product needs to performs its owns testing and obtains its owns certificates.
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20CE%20certification-S21051101701001.pdf Quartz64 model-A CE Certificate]
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20FCC%20certification-S21051101702001.pdf Quartz64 model-A FCC Certificate]

=== Model "B" ===

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID center-positive Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf Quartz64 Model "B" SBC Schematic ver 1.3 20220124 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_PCB_Components_Placement-V1.2_20211014.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]
* Please note that v1.2 and V1.3 schematic and component placement are identical, just some component value changed.

* Note: Model B uses a Molex PicoBlade compatible connector for the RTC battery. The Pine64 Backup Battery Holders come with a JST PH type connector. To use the Pine64 RTC Backup Battery Holder, the connector on the battery holder will need to be modified with a PicoBlade type connector.

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK817%20datasheet%20V1.01.pdf Rockchip RK817 ver 1.01 datasheet for Quartz64 model A]
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for Quartz64 model B and SOQuartz]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
** [https://files.pine64.org/doc/datasheet/PineNote/TI%20PMU-TPS651851.pdf TPS65185x PMIC for E-Ink Enabled Electronic Paper Display Datasheet]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]
* IR LED:
** [https://media.digikey.com/pdf/Data%20Sheets/Everlight%20PDFs/IRM-36xx_Series.pdf IRM-3638 Datasheet]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
** [https://www.printables.com/model/269572-pine-quartz-64-a-full-case 3D Printable Enclosure for Model A]
** [https://www.printables.com/model/269575-pine-quartz-64-a-open-frame Open Frame for Model A]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port (Model A)]
** [https://www.molex.com/pdm_docs/sd/533980271_sd.pdf 1.25mm Picoblade Type connector specification used in RTC Battery port (Model B)]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

=== Android 11 Production Test Build for Quartz64 model A SBC ===

==== Android 11 Stock Image [eMMC Boot] using DD method [20210604] ====
* DD image to eMMC module using USB adapter for eMMC module and boot. Highly recommend using [https://etcher.io/ Etcher]
* This is test build that used during product testing
* Please allow 3-5 minutes boot up time on first time for initialization
* DD image for 8GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-8GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): e4365753e584d9fce1b8f10f095eede6
*** File Size: 819MB
* DD image for 16GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-16GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 491c5f7744b0ca0b74ae76e607051836
*** File Size: 1.10GB
* DD image for 32GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-32GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 47a6f0cdac8bad06cb920743849a8894
*** File Size: 846MB
* DD image for 64GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-64GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 4e2fed6f5db0d55afdc8a142fc0c4fe1
*** File Size: 884MB

==== Android 11 Production Test Build for Quartz64 model A SBC [eMMC Boot] using ROCKChip tools method [20210604] ====
* Please unzip first and then using [https://files.pine64.org/os/Quartz64//android/RKDevTool_Release_v2.84.zip Rockchip Android tool ver 2.84] to flash in
* For Windows OS environment, please install the [https://files.pine64.org/os/Quartz64/android/DriverAssitant_v5.1.1.zip DriverAssistant v5.11] driver first
* This is test build that used during product testing
* The OTG port located at top USB 2.0 port on top of USB 3.0 port, needs USB type A to type A cable.
* Please allow 3-5 minutes boot up time on first time for initialization
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_20210604_stock_android11_emmcboot.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 800f867fdd0d1b2bd7822c156b6067e3
*** File Size: 812MB

=== Android 11 eink SDK for Quartz64 model A SBC ===
* The is the Android SDK build for 10.3" eink panel on Quartz64 model A SBC.
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_eink.android11_SDK.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 293a550584298de4fb95ceae18103672
** File Size: 72.88GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Enclosures ==

(Please expand this section with more cases known to work.)

=== Model "A" ===

All enclosures that fit the ROCKPro64 should fit the Quartz64 Model "A", as the I/O has been laid out the same on purpose.

* [["Model A" Acrylic Open Enclosure]] - but see the troubleshooting section below.
* [[ROCKPro64 ABS Enclosure]]
* [[Quartz64PremiumAluminiumCase|RockPro64 Premium Aluminium Case]]
* [[ROCKPro64#3D_printable_ITX_mounting_brackets]] (Not an enclosure but allows to mount the board in an ATX/ITX case)

=== Model "B" ===

* [["Model B" Acrylic Open Enclosure]]
* the ROCK64 aluminium enclosure '''does not''' work, as the DC input jack is placed differently

== Troubleshooting ==

=== Stability/Boot Issues With Missing Battery Shunt ===

If there is no battery plugged into the board, the jumper labelled "ON/OFF_BATT" must be in place. If this is set wrong, stability issues such as failures to boot will occur.

=== No Ethernet Connectivity ===

Make sure the kernel is built with <code>CONFIG_MOTORCOMM_PHY</code> set to <code>y</code>. Building it as a module (<code>m</code>) and then relying on module auto-loading is unlikely to work, because if the generic PHY driver is built in it will bind to the PHY first, unless you include the motorcomm module in your initramfs.

=== "Model A" Acrylic Case Doesn't Fit ===

The Quartz64 does not really fit onto the bottom plate of the [["Model A" Acrylic Open Enclosure]]. This is because the "Mic" connector at the bottom of the board interferes with one of the posts. A workaround is to find out which post that is (you have a 50% chance of guessing it right, accounting for rotating the board) and then filing away the corner of the post pointing inwards by a few millimetres.

[[File:Quartz64-audio-jack-spacer-issue.jpg]]

An alternate solution may be to place plastic spacers with a smaller outer diameter in between the acrylic bottom plate posts and the SBC board.

=== No GPU Acceleration with Debian "Bullseye" Userland ===

Debian Bullseye ships a Mesa version that is too old to contain the required patches for the RK356x SoC's GPU. You can (at your own risk) [https://wiki.debian.org/DebianTesting use the current Debian Testing version ], called "Bookworm".

=== Wireless Connectivity Doesn't Work ===

ROCKPro64 wireless module may have CYW43455 or CYW43456 chips on board (not sure if this is the same for Quartz64 model B). Both chips are supported by <code>brcmfmac</code> wi-fi driver and <code>btbcm</code> bluetooth driver.

For CYW43455 drivers attempt to load <code>/lib/firmware/brcm/brcmfmac43455-sdio.bin</code> for wi-fi and <code>/lib/firmware/brcm/BCM4345C0.hcd</code> for bluetooth. Corresponding firmware files for CYW43456 are <code>/lib/firmware/brcm/brcmfmac43456-sdio.bin</code> and <code>/lib/firmware/brcm/BCM4345C5.hcd</code>.

On Manjaro firmware files for both bluetooth and wi-fi on CYW43456 on are provided by <code>ap6256-firmware</code> package (<code>pacman -S ap6256-firmware</code>).

However for CYW43455 wi-fi firmware is in the <code>linux-firmware</code> package and bluetooth is in the <code>firmware-raspberrypi</code> (<code>pacman -S linux-firmware firmware-raspberrypi</code>). <code>linux-firmware</code> package is missing device specific symlinks for quartz64-a. To create them execute:
# ln -s brcmfmac43455-sdio.bin /lib/firmware/brcm/brcmfmac43455-sdio.pine64,quartz64-a.bin
# ln -s brcmfmac43455-sdio.AW-CM256SM.txt /lib/firmware/brcm/brcmfmac43455-sdio.pine64,quartz64-a.txt

As of 2022-09-25 device tree in mainline kernel for Quartz64 model A has wrong configuration for the bluetooth driver. [https://patchwork.kernel.org/project/linux-rockchip/patch/20220925124825.71786-1-leo@nabam.net/ Patch] is submitted to the LKML. It's possible to modify dtb file provided by the current kernel using device tree compiler to enable bluetooth or perform <code>make dtbs</code> in the patched kernel tree to get updated dtb file (<code>arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dtb</code>).

== How-To ==

=== Connect Debug UART ===

The easiest way to get debug output is to connect a 3.3V 1.5mbaud capable UART adapter to the board.

To connect it, connect the ground lead to pin 6, and the RX/TX leads to pins 8 and 10 (consider swapping them if you get no output, things are often mislabelled). These pins are "UART2" in the above GPIO table.

Open a serial terminal at 1500000 bauds, e.g.

$ picocom -b 1500000 /dev/ttyUSB0

=== Disable Heartbeat LED (Linux) ===

The flashing LED is called the "heartbeat LED", it blinks in a heart rhythm like fashion once the kernel is running. To disable it, you can run

# echo none > /sys/class/leds/user-led/trigger

On model A LED device is called "diy-led", not "user-led".

On a system with systemd, you can do this as soon as the system is ready to be logged in with a systemd unit like this:

[Unit]
Description=Turn off heartbeat LED
Wants=multi-user.target
After=multi-user.target

[Install]
WantedBy=multi-user.target

[Service]
Type=simple
ExecStart=sh -c 'echo none > /sys/class/leds/user-led/trigger'

Place it in <tt>/etc/systemd/system/user-led.service</tt>, and run

# systemctl daemon-reload
# systemctl enable user-led.service

Upon rebooting, you will now notice that the heartbeat LED will blink during boot-up, but stops blinking as soon as the multi-user target is reached (i.e. the user can log in).

=== SATA on model A ===

On model A USB 3.0 and SATA ports are using the same I/O line and can't be used simultaneously. By default USB 3.0 is enabled in linux device tree and SATA is disabled. FDT modifications are required to turn SATA on.

Following script is tested on Monjaro but should work on the other distros with minimal changes. Device tree compiler package usually provides fdtput command (on Manjaro run: <code> pacman -S dtc</code>)

# cp /boot/dtbs/rockchip/rk3566-quartz64-a.dtb /boot/dtbs/rockchip/rk3566-quartz64-a-sata.dtb
# fdtput -t s -v /boot/dtbs/rockchip/rk3566-quartz64-a-sata.dtb /usb@fd000000 status disabled
# fdtput -t s -v /boot/dtbs/rockchip/rk3566-quartz64-a-sata.dtb /sata@fc400000 status okay
# sed -i 's#^FDT /dtbs/rockchip/rk3566-quartz64-a.dtb$#FDT /dtbs/rockchip/rk3566-quartz64-a-sata.dtb#' /boot/extlinux/extlinux.conf
# systemctl reboot

[[Category:Quartz64]]

Quartz64

2022-09-09T12:54:49Z

Davelong: Update RTC connector information

[[File:Quartz64modelb.png|400px|thumb|right|The Quartz64 Model B]]

The '''Quartz64''' is the most recent Single Board Computer offering from PINE64, with Model A initially released in June of 2021 and Model B in May of 2022. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software releases ==

{{warning|Software for the Quartz64 is still early in development, and therefore currently lacks features such as the ability to produce video output. You are strongly encouraged to procure a 3.3V UART serial adapter capable of running at 1.5 mbauds, such as [https://pine64.com/product/serial-console-woodpecker-edition/ the woodpecker] if you want to use a Quartz64 at this stage.}}
{{note|'''Note:''' OS images are provided by the community, not by PINE64. Most community projects currently aim at getting mainline Linux running on the board, not some vendor provided kernel that will never be receiving updates. A mainline-first approach allows for the boards to continue receiving important updates, such as security updates, for years to come, as well as have higher quality code in the kernel as it underwent independent review, but does mean that not all aspects of the hardware work right out of the gate.}}

=== Armbian ===
[[File:armbian.png|right|100px]]

Armbian is a base operating system platform for single board computers

* Lightweight Debian or Ubuntu based Linux distribution specialised for ARM development boards
* Each system is compiled, assembled and optimised by [https://github.com/armbian/build Armbian Build Tools]
* It has powerful build and software development tools to make custom builds

Download [https://github.com/armbian/build/releases/ latest, as fresh as possible, upon code change, images]

Support on Armbian forums https://forum.armbian.com/forum/96-upcoming-hardware-wip/

=== Manjaro ARM ===
[[File:Manjaro.png|right|100px]]

Manjaro ARM is a user friendly rolling release distribution, based on Arch Linux ARM.

==== Manjaro ARM with no desktop ====

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
Note, manjaro currently ships with the linux-rc kernel. Currently (and temporarily/as of writing), usb3, pcie and sata devices will not be found unless you swap to the linux-quartz64 kernel <code>pacman -S linux-quartz64</code>.
* [https://github.com/manjaro-arm/quartz64-a-images/releases Images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

==== Manjaro ARM with desktop environment ====

Since '''Dev 20211117''' with hdmi output (linux-rc)

* Gnome
* KDE Plasma
* Mate
* Sway
* XFCE

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

=== pgwipeout's Quartz64 CI ===

pgwipeout provides continuously rebuilt set of images for Quartz64 devices which includes a Debian installer and a buildroot rescue environment. It is aimed at advanced users who generally know their way around a Linux system, and as a baseline for whether something is working or not. Works on both SD cards and eMMC, uses pgwipeout's patched kernel. Kernels aren't auto-updated on the installed system, so the user manually has to do this by mounting the actual correct boot partition.

'''Download:''' https://gitlab.com/pgwipeout/quartz64_ci/-/pipelines (Click the three dots on the right, download the merge-job archive.)

For Quartz64 Model A, flash <tt>rk3566-quartz64-a.dtb.img.xz</tt>. On Linux, you can for example do this as follows, assuming your target device is <tt>/dev/sdX</tt>:

sudo -i; xzcat /path/to/rk3566-quartz64-a.dtb.img.xz > /dev/sdX

For Quartz64 Model B, use <tt>rk3566-quartz64-b.dtb.img.xz</tt> instead.

For line by line instructions to boot Quartz64 CI on a microSD card and use it to install Debian onto an eMMC follow these instructions https://wiki.pine64.org/wiki/Installing_Debian_on_the_Quartz64

=== Arch Linux ARM (Unofficial) ===

See [[Installing Arch Linux ARM On The Quartz64]] for detailed instructions.

=== Tianocore EDK II port by jmcneill ===

This (as of 2021-12-30) is a work in progress to enable UEFI enabled systems, and is able to bring up SD, eMMC, USB, PCIe with SATA and NVMe, HDMI, thermal sensors, TRNG, as well as general Cortex A-55 features. Known to work with NetBSD -current, and the ESXi Arm fling version 1.8.

* [https://github.com/jaredmcneill/quartz64_uefi jmcneill's Quartz64 UEFI Github]

The sdcard image should be written to an microSD card and installed. Currently, using this card also for the OS may be problematic.

=== NetBSD ===

NetBSD relies upon the UEFI support in Tianocore. Before NetBSD 10 is released, the latest version of NetBSD-current should be used:

* [http://nycdn.netbsd.org/pub/NetBSD-daily/HEAD/ NetBSD daily builds top level] from inside here, navigate to a date, and inside the images/ subdirectory are installable images. Use the one called "NetBSD-<version>-evbarm-aarch64-install.img.gz". This image can be written to a supported device, such as the eMMC interface, any USB storage device, NVMe, and PCIe AHCI SATA are all supported with builds after 2022-01-15.

* Currently this can not be shared with the EDK2 port, ie, microSD for EDK2 and some other media for NetBSD.

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support
* [https://www.cnx-software.com/2020/12/01/rockchip-rk3568-processor-to-power-edge-computing-and-nvr-applications 22nm process, believed to be FD-SOI]

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB (SOQuartz only), 4GB, 8GB LPDDR4.

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB
** Model A: 2 USB 2.0 host ports, 1 USB 2.0 OTG port, 1 USB 3.0 host port
** Model B: 1 USB 2.0 host port, 1 USB 2.0 OTG port, 1 USB 3.0 host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 8GB up to 128GB
* 64 Mbit (8 MByte) SPI flash (Model B only), part number <tt>25Q64DWZPIG</tt> in the schematic

==== eMMC Speeds ====

On a 64 GB eMMC module:

$ sudo hdparm -tT /dev/mmcblk1

/dev/mmcblk1:
Timing cached reads: 2368 MB in 2.00 seconds = 1184.46 MB/sec
Timing buffered disk reads: 452 MB in 3.01 seconds = 149.98 MB/sec

=== Expansion Ports ===
* HDMI
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints
** On Model A, the slot provides 10W of power for the 3.3V supply and however much power your 12V input power supply provides on the 12V supply

The PCIe implementation on the RK3566 is much more compatible with a wide range of devices compared to the one on the RK3399 used on the ROCKPro64. This means a lot more devices should work (excluding dGPUs due to a lack of cache snooping ability).

==== Combo PHYs ====

[[File:rk3566 phy.png]]

Several of the I/O options on the RK3566 used in the Quartz64 are using the same I/O lines, meaning that they cannot be used at the same time. The above diagram illustrates how they are connected.

In particular, USB 3.0 and the SATA connector on the board are mutually exclusive, and the PCI-e 2.0 lane can be reconfigured into a second SATA port, though an adapter cable needs to be fashioned for this to be useful.

=== GPIO Pins (Quartz64 Model A) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin no.
! scope="col" | Pin no.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX a
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX a
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT c
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

====Notes====
<ol style="list-style-type:lower-alpha">
<li>can be a PWM pin</li>
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
<li>low-pass filtered with cutoff of 220 MHz</li>
</ol>

Source: Page 28 of [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf the board schematics].

=== GPIO Pins (Quartz64 Model B) ===

Attention! GPIOs are 3.3V!

Interesting alternate pin configurations are listed in [brackets].

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin no.
! scope="col" | Pin no.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 1
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| ''[I2C3_SDA_M0]'' GPIO1_A0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| ''[I2C3_SCL_M0]'' GPIO1_A1_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_C4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX
|-
| style="text-align:right;"| ''[SPI1_CS0_M1]'' GPIO3_A1_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| GPIO3_A3_3V3
|-
| style="text-align:right;"| GPIO3_A2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GPIO3_B1_3V3
|-
| style="text-align:right;"| 3.3V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 17
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| GPIO3_B2_3V3
|-
| style="text-align:right;"| GPIO4_C3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO4_C5_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 21
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 22
| style="text-align:left;"| GPIO3_C1_3V3 ''[SPI1_MOSI_M1]''
|-
| style="text-align:right;"| GPIO4_C2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 23
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 24
| style="text-align:left;"| GPIO4_C6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 25
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 26
| style="text-align:left;"| GPIO4_D1_3V3
|-
| style="text-align:right;"| I2C4_SDA_M0
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 27
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 28
| style="text-align:left;"| I2C4_SCL_M0
|-
| style="text-align:right;"| GPIO3_B3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 29
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 30
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 31
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 32
| style="text-align:left;"| GPIO3_C2_3V3 ''[SPI1_MISO_M1]''
|-
| style="text-align:right;"| ''[SPI1_CLK_M1]'' GPIO3_C3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 33
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 34
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 35
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 36
| style="text-align:left;"| GPIO3_A7_3V3
|-
| style="text-align:right;"| ''[SPDIF_TX_M0]'' GPIO1_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 37
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 38
| style="text-align:left;"| GPIO3_A6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 39
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 40
| style="text-align:left;"| GPIO3_A5_3V3
|}

Source: Page 24 of [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf the board schematics].

== Quartz64 Board Information, Schematics, and Certifications ==

=== Model "A" ===
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Quartz64 Model "A" SBC Schematic ver 2.0 20210427 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V2.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Certifications:
** Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary. However, PINE64 still submit the SBC for FCC and CE certification and obtain the certificates to proof that SBC board is capable on passing the testing. Please note a final commercial product needs to performs its owns testing and obtains its owns certificates.
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20CE%20certification-S21051101701001.pdf Quartz64 model-A CE Certificate]
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20FCC%20certification-S21051101702001.pdf Quartz64 model-A FCC Certificate]

=== Model "B" ===

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID center-positive Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf Quartz64 Model "B" SBC Schematic ver 1.3 20220124 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_PCB_Components_Placement-V1.2_20211014.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]
* Please note that v1.2 and V1.3 schematic and component placement are identical, just some component value changed.

* Note: Model B uses a Molex PicoBlade compatible connector for the RTC battery. The Pine64 Backup Battery Holders come with a JST PH type connector. To use the Pine64 RTC Backup Battery Holder, the connector on the battery holder will need to be modified with a PicoBlade type connector.

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK817%20datasheet%20V1.01.pdf Rockchip RK817 ver 1.01 datasheet for Quartz64 model A]
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for Quartz64 model B and SOQuartz]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
** [https://files.pine64.org/doc/datasheet/PineNote/TI%20PMU-TPS651851.pdf TPS65185x PMIC for E-Ink Enabled Electronic Paper Display Datasheet]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
** [https://www.printables.com/model/269572-pine-quartz-64-a-full-case 3D Printable Enclosure for Model A]
** [https://www.printables.com/model/269575-pine-quartz-64-a-open-frame Open Frame for Model A]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port (Model A)]
** [https://www.molex.com/pdm_docs/sd/533980271_sd.pdf 1.25mm Picoblade Type connector specification used in RTC Battery port (Model B)]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

=== Android 11 Production Test Build for Quartz64 model A SBC ===

==== Android 11 Stock Image [eMMC Boot] using DD method [20210604] ====
* DD image to eMMC module using USB adapter for eMMC module and boot. Highly recommend using [https://etcher.io/ Etcher]
* This is test build that used during product testing
* Please allow 3-5 minutes boot up time on first time for initialization
* DD image for 8GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-8GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): e4365753e584d9fce1b8f10f095eede6
*** File Size: 819MB
* DD image for 16GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-16GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 491c5f7744b0ca0b74ae76e607051836
*** File Size: 1.10GB
* DD image for 32GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-32GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 47a6f0cdac8bad06cb920743849a8894
*** File Size: 846MB
* DD image for 64GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-64GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 4e2fed6f5db0d55afdc8a142fc0c4fe1
*** File Size: 884MB

==== Android 11 Production Test Build for Quartz64 model A SBC [eMMC Boot] using ROCKChip tools method [20210604] ====
* Please unzip first and then using [https://files.pine64.org/os/Quartz64//android/RKDevTool_Release_v2.84.zip Rockchip Android tool ver 2.84] to flash in
* For Windows OS environment, please install the [https://files.pine64.org/os/Quartz64/android/DriverAssitant_v5.1.1.zip DriverAssistant v5.11] driver first
* This is test build that used during product testing
* The OTG port located at top USB 2.0 port on top of USB 3.0 port, needs USB type A to type A cable.
* Please allow 3-5 minutes boot up time on first time for initialization
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_20210604_stock_android11_emmcboot.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 800f867fdd0d1b2bd7822c156b6067e3
*** File Size: 812MB

=== Android 11 eink SDK for Quartz64 model A SBC ===
* The is the Android SDK build for 10.3" eink panel on Quartz64 model A SBC.
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_eink.android11_SDK.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 293a550584298de4fb95ceae18103672
** File Size: 72.88GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Enclosures ==

(Please expand this section with more cases known to work.)

=== Model "A" ===

All enclosures that fit the ROCKPro64 should fit the Quartz64 Model "A", as the I/O has been laid out the same on purpose.

* [["Model A" Acrylic Open Enclosure]] - but see the troubleshooting section below.
* [[ROCKPro64 ABS Enclosure]]
* [[Quartz64PremiumAluminiumCase|RockPro64 Premium Aluminium Case]]
* [[ROCKPro64#3D_printable_ITX_mounting_brackets]] (Not an enclosure but allows to mount the board in an ATX/ITX case)

=== Model "B" ===

* [["Model B" Acrylic Open Enclosure]]
* the ROCK64 aluminium enclosure '''does not''' work, as the DC input jack is placed differently

== Troubleshooting ==

=== Stability/Boot Issues With Missing Battery Shunt ===

If there is no battery plugged into the board, the jumper labelled "ON/OFF_BATT" must be in place. If this is set wrong, stability issues such as failures to boot will occur.

=== No Ethernet Connectivity ===

Make sure the kernel is built with <code>CONFIG_MOTORCOMM_PHY</code> set to <code>y</code>. Building it as a module (<code>m</code>) and then relying on module auto-loading is unlikely to work, because if the generic PHY driver is built in it will bind to the PHY first, unless you include the motorcomm module in your initramfs.

=== "Model A" Acrylic Case Doesn't Fit ===

The Quartz64 does not really fit onto the bottom plate of the [["Model A" Acrylic Open Enclosure]]. This is because the "Mic" connector at the bottom of the board interferes with one of the posts. A workaround is to find out which post that is (you have a 50% chance of guessing it right, accounting for rotating the board) and then filing away the corner of the post pointing inwards by a few millimetres.

[[File:Quartz64-audio-jack-spacer-issue.jpg]]

An alternate solution may be to place plastic spacers with a smaller outer diameter in between the acrylic bottom plate posts and the SBC board.

=== No GPU Acceleration with Debian "Bullseye" Userland ===

Debian Bullseye ships a Mesa version that is too old to contain the required patches for the RK356x SoC's GPU. You can (at your own risk) [https://wiki.debian.org/DebianTesting use the current Debian Testing version ], called "Bookworm".

== How-To ==

=== Connect Debug UART ===

The easiest way to get debug output is to connect a 3.3V 1.5mbaud capable UART adapter to the board.

To connect it, connect the ground lead to pin 6, and the RX/TX leads to pins 8 and 10 (consider swapping them if you get no output, things are often mislabelled). These pins are "UART2" in the above GPIO table.

Open a serial terminal at 1500000 bauds, e.g.

$ picocom -b 1500000 /dev/ttyUSB0

=== Disable Heartbeat LED (Linux) ===

The flashing LED is called the "heartbeat LED", it blinks in a heart rhythm like fashion once the kernel is running. To disable it, you can run

# echo none > /sys/class/leds/user-led/trigger

On a system with systemd, you can do this as soon as the system is ready to be logged in with a systemd unit like this:

[Unit]
Description=Turn off heartbeat LED
Wants=multi-user.target
After=multi-user.target

[Install]
WantedBy=multi-user.target

[Service]
Type=simple
ExecStart=sh -c 'echo none > /sys/class/leds/user-led/trigger'

Place it in <tt>/etc/systemd/system/user-led.service</tt>, and run

# systemctl daemon-reload
# systemctl enable user-led.service

Upon rebooting, you will now notice that the heartbeat LED will blink during boot-up, but stops blinking as soon as the multi-user target is reached (i.e. the user can log in).

[[Category:Quartz64]]

Quartz64

2022-09-09T02:25:54Z

Davelong:

[[File:Quartz64modelb.png|400px|thumb|right|The Quartz64 Model B]]

The '''Quartz64''' is the most recent Single Board Computer offering from PINE64, with Model A initially released in June of 2021 and Model B in May of 2022. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software releases ==

{{warning|Software for the Quartz64 is still early in development, and therefore currently lacks features such as the ability to produce video output. You are strongly encouraged to procure a 3.3V UART serial adapter capable of running at 1.5 mbauds, such as [https://pine64.com/product/serial-console-woodpecker-edition/ the woodpecker] if you want to use a Quartz64 at this stage.}}
{{note|'''Note:''' OS images are provided by the community, not by PINE64. Most community projects currently aim at getting mainline Linux running on the board, not some vendor provided kernel that will never be receiving updates. A mainline-first approach allows for the boards to continue receiving important updates, such as security updates, for years to come, as well as have higher quality code in the kernel as it underwent independent review, but does mean that not all aspects of the hardware work right out of the gate.}}

=== Armbian ===
[[File:armbian.png|right|100px]]

Armbian is a base operating system platform for single board computers

* Lightweight Debian or Ubuntu based Linux distribution specialised for ARM development boards
* Each system is compiled, assembled and optimised by [https://github.com/armbian/build Armbian Build Tools]
* It has powerful build and software development tools to make custom builds

Download [https://github.com/armbian/build/releases/ latest, as fresh as possible, upon code change, images]

Support on Armbian forums https://forum.armbian.com/forum/96-upcoming-hardware-wip/

=== Manjaro ARM ===
[[File:Manjaro.png|right|100px]]

Manjaro ARM is a user friendly rolling release distribution, based on Arch Linux ARM.

==== Manjaro ARM with no desktop ====

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
Note, manjaro currently ships with the linux-rc kernel. Currently (and temporarily/as of writing), usb3, pcie and sata devices will not be found unless you swap to the linux-quartz64 kernel <code>pacman -S linux-quartz64</code>.
* [https://github.com/manjaro-arm/quartz64-a-images/releases Images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

==== Manjaro ARM with desktop environment ====

Since '''Dev 20211117''' with hdmi output (linux-rc)

* Gnome
* KDE Plasma
* Mate
* Sway
* XFCE

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

=== pgwipeout's Quartz64 CI ===

pgwipeout provides continuously rebuilt set of images for Quartz64 devices which includes a Debian installer and a buildroot rescue environment. It is aimed at advanced users who generally know their way around a Linux system, and as a baseline for whether something is working or not. Works on both SD cards and eMMC, uses pgwipeout's patched kernel. Kernels aren't auto-updated on the installed system, so the user manually has to do this by mounting the actual correct boot partition.

'''Download:''' https://gitlab.com/pgwipeout/quartz64_ci/-/pipelines (Click the three dots on the right, download the merge-job archive.)

For Quartz64 Model A, flash <tt>rk3566-quartz64-a.dtb.img.xz</tt>. On Linux, you can for example do this as follows, assuming your target device is <tt>/dev/sdX</tt>:

sudo -i; xzcat /path/to/rk3566-quartz64-a.dtb.img.xz > /dev/sdX

For Quartz64 Model B, use <tt>rk3566-quartz64-b.dtb.img.xz</tt> instead.

For line by line instructions to boot Quartz64 CI on a microSD card and use it to install Debian onto an eMMC follow these instructions https://wiki.pine64.org/wiki/Installing_Debian_on_the_Quartz64

=== Arch Linux ARM (Unofficial) ===

See [[Installing Arch Linux ARM On The Quartz64]] for detailed instructions.

=== Tianocore EDK II port by jmcneill ===

This (as of 2021-12-30) is a work in progress to enable UEFI enabled systems, and is able to bring up SD, eMMC, USB, PCIe with SATA and NVMe, HDMI, thermal sensors, TRNG, as well as general Cortex A-55 features. Known to work with NetBSD -current, and the ESXi Arm fling version 1.8.

* [https://github.com/jaredmcneill/quartz64_uefi jmcneill's Quartz64 UEFI Github]

The sdcard image should be written to an microSD card and installed. Currently, using this card also for the OS may be problematic.

=== NetBSD ===

NetBSD relies upon the UEFI support in Tianocore. Before NetBSD 10 is released, the latest version of NetBSD-current should be used:

* [http://nycdn.netbsd.org/pub/NetBSD-daily/HEAD/ NetBSD daily builds top level] from inside here, navigate to a date, and inside the images/ subdirectory are installable images. Use the one called "NetBSD-<version>-evbarm-aarch64-install.img.gz". This image can be written to a supported device, such as the eMMC interface, any USB storage device, NVMe, and PCIe AHCI SATA are all supported with builds after 2022-01-15.

* Currently this can not be shared with the EDK2 port, ie, microSD for EDK2 and some other media for NetBSD.

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support
* [https://www.cnx-software.com/2020/12/01/rockchip-rk3568-processor-to-power-edge-computing-and-nvr-applications 22nm process, believed to be FD-SOI]

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB (SOQuartz only), 4GB, 8GB LPDDR4.

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB
** Model A: 2 USB 2.0 host ports, 1 USB 2.0 OTG port, 1 USB 3.0 host port
** Model B: 1 USB 2.0 host port, 1 USB 2.0 OTG port, 1 USB 3.0 host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 8GB up to 128GB
* 64 Mbit (8 MByte) SPI flash (Model B only), part number <tt>25Q64DWZPIG</tt> in the schematic

==== eMMC Speeds ====

On a 64 GB eMMC module:

$ sudo hdparm -tT /dev/mmcblk1

/dev/mmcblk1:
Timing cached reads: 2368 MB in 2.00 seconds = 1184.46 MB/sec
Timing buffered disk reads: 452 MB in 3.01 seconds = 149.98 MB/sec

=== Expansion Ports ===
* HDMI
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints
** On Model A, the slot provides 10W of power for the 3.3V supply and however much power your 12V input power supply provides on the 12V supply

The PCIe implementation on the RK3566 is much more compatible with a wide range of devices compared to the one on the RK3399 used on the ROCKPro64. This means a lot more devices should work (excluding dGPUs due to a lack of cache snooping ability).

==== Combo PHYs ====

[[File:rk3566 phy.png]]

Several of the I/O options on the RK3566 used in the Quartz64 are using the same I/O lines, meaning that they cannot be used at the same time. The above diagram illustrates how they are connected.

In particular, USB 3.0 and the SATA connector on the board are mutually exclusive, and the PCI-e 2.0 lane can be reconfigured into a second SATA port, though an adapter cable needs to be fashioned for this to be useful.

=== GPIO Pins (Quartz64 Model A) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin no.
! scope="col" | Pin no.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX a
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX a
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT c
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

====Notes====
<ol style="list-style-type:lower-alpha">
<li>can be a PWM pin</li>
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
<li>low-pass filtered with cutoff of 220 MHz</li>
</ol>

Source: Page 28 of [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf the board schematics].

=== GPIO Pins (Quartz64 Model B) ===

Attention! GPIOs are 3.3V!

Interesting alternate pin configurations are listed in [brackets].

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin no.
! scope="col" | Pin no.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 1
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| ''[I2C3_SDA_M0]'' GPIO1_A0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| ''[I2C3_SCL_M0]'' GPIO1_A1_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_C4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX
|-
| style="text-align:right;"| ''[SPI1_CS0_M1]'' GPIO3_A1_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| GPIO3_A3_3V3
|-
| style="text-align:right;"| GPIO3_A2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GPIO3_B1_3V3
|-
| style="text-align:right;"| 3.3V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 17
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| GPIO3_B2_3V3
|-
| style="text-align:right;"| GPIO4_C3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO4_C5_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 21
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 22
| style="text-align:left;"| GPIO3_C1_3V3 ''[SPI1_MOSI_M1]''
|-
| style="text-align:right;"| GPIO4_C2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 23
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 24
| style="text-align:left;"| GPIO4_C6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 25
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 26
| style="text-align:left;"| GPIO4_D1_3V3
|-
| style="text-align:right;"| I2C4_SDA_M0
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 27
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 28
| style="text-align:left;"| I2C4_SCL_M0
|-
| style="text-align:right;"| GPIO3_B3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 29
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 30
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 31
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 32
| style="text-align:left;"| GPIO3_C2_3V3 ''[SPI1_MISO_M1]''
|-
| style="text-align:right;"| ''[SPI1_CLK_M1]'' GPIO3_C3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 33
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 34
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 35
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 36
| style="text-align:left;"| GPIO3_A7_3V3
|-
| style="text-align:right;"| ''[SPDIF_TX_M0]'' GPIO1_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 37
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 38
| style="text-align:left;"| GPIO3_A6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 39
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 40
| style="text-align:left;"| GPIO3_A5_3V3
|}

Source: Page 24 of [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf the board schematics].

== Quartz64 Board Information, Schematics, and Certifications ==

=== Model "A" ===
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Quartz64 Model "A" SBC Schematic ver 2.0 20210427 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V2.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Certifications:
** Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary. However, PINE64 still submit the SBC for FCC and CE certification and obtain the certificates to proof that SBC board is capable on passing the testing. Please note a final commercial product needs to performs its owns testing and obtains its owns certificates.
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20CE%20certification-S21051101701001.pdf Quartz64 model-A CE Certificate]
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20FCC%20certification-S21051101702001.pdf Quartz64 model-A FCC Certificate]

=== Model "B" ===

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID center-positive Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf Quartz64 Model "B" SBC Schematic ver 1.3 20220124 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_PCB_Components_Placement-V1.2_20211014.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]
* Please note that v1.2 and V1.3 schematic and component placement are identical, just some component value changed.

* Note: Model B uses a GH type connector for the RTC battery. The Pine64 Backup Battery Holders come with a PH type connector. To use the Pine64 RTC Backup Battery Holder, the connector on the battery holder will need to be modified with a GH type connector.

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK817%20datasheet%20V1.01.pdf Rockchip RK817 ver 1.01 datasheet for Quartz64 model A]
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for Quartz64 model B and SOQuartz]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
** [https://files.pine64.org/doc/datasheet/PineNote/TI%20PMU-TPS651851.pdf TPS65185x PMIC for E-Ink Enabled Electronic Paper Display Datasheet]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
** [https://www.printables.com/model/269572-pine-quartz-64-a-full-case 3D Printable Enclosure for Model A]
** [https://www.printables.com/model/269575-pine-quartz-64-a-open-frame Open Frame for Model A]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port (Model A)]
** [https://www.jst-mfg.com/product/pdf/eng/eGH.pdf 1.25mm GH Type connector specification used in RTC Battery port (Model B)]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

=== Android 11 Production Test Build for Quartz64 model A SBC ===

==== Android 11 Stock Image [eMMC Boot] using DD method [20210604] ====
* DD image to eMMC module using USB adapter for eMMC module and boot. Highly recommend using [https://etcher.io/ Etcher]
* This is test build that used during product testing
* Please allow 3-5 minutes boot up time on first time for initialization
* DD image for 8GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-8GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): e4365753e584d9fce1b8f10f095eede6
*** File Size: 819MB
* DD image for 16GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-16GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 491c5f7744b0ca0b74ae76e607051836
*** File Size: 1.10GB
* DD image for 32GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-32GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 47a6f0cdac8bad06cb920743849a8894
*** File Size: 846MB
* DD image for 64GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-64GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 4e2fed6f5db0d55afdc8a142fc0c4fe1
*** File Size: 884MB

==== Android 11 Production Test Build for Quartz64 model A SBC [eMMC Boot] using ROCKChip tools method [20210604] ====
* Please unzip first and then using [https://files.pine64.org/os/Quartz64//android/RKDevTool_Release_v2.84.zip Rockchip Android tool ver 2.84] to flash in
* For Windows OS environment, please install the [https://files.pine64.org/os/Quartz64/android/DriverAssitant_v5.1.1.zip DriverAssistant v5.11] driver first
* This is test build that used during product testing
* The OTG port located at top USB 2.0 port on top of USB 3.0 port, needs USB type A to type A cable.
* Please allow 3-5 minutes boot up time on first time for initialization
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_20210604_stock_android11_emmcboot.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 800f867fdd0d1b2bd7822c156b6067e3
*** File Size: 812MB

=== Android 11 eink SDK for Quartz64 model A SBC ===
* The is the Android SDK build for 10.3" eink panel on Quartz64 model A SBC.
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_eink.android11_SDK.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 293a550584298de4fb95ceae18103672
** File Size: 72.88GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Enclosures ==

(Please expand this section with more cases known to work.)

=== Model "A" ===

All enclosures that fit the ROCKPro64 should fit the Quartz64 Model "A", as the I/O has been laid out the same on purpose.

* [["Model A" Acrylic Open Enclosure]] - but see the troubleshooting section below.
* [[ROCKPro64 ABS Enclosure]]
* [[Quartz64PremiumAluminiumCase|RockPro64 Premium Aluminium Case]]
* [[ROCKPro64#3D_printable_ITX_mounting_brackets]] (Not an enclosure but allows to mount the board in an ATX/ITX case)

=== Model "B" ===

* [["Model B" Acrylic Open Enclosure]]
* the ROCK64 aluminium enclosure '''does not''' work, as the DC input jack is placed differently

== Troubleshooting ==

=== Stability/Boot Issues With Missing Battery Shunt ===

If there is no battery plugged into the board, the jumper labelled "ON/OFF_BATT" must be in place. If this is set wrong, stability issues such as failures to boot will occur.

=== No Ethernet Connectivity ===

Make sure the kernel is built with <code>CONFIG_MOTORCOMM_PHY</code> set to <code>y</code>. Building it as a module (<code>m</code>) and then relying on module auto-loading is unlikely to work, because if the generic PHY driver is built in it will bind to the PHY first, unless you include the motorcomm module in your initramfs.

=== "Model A" Acrylic Case Doesn't Fit ===

The Quartz64 does not really fit onto the bottom plate of the [["Model A" Acrylic Open Enclosure]]. This is because the "Mic" connector at the bottom of the board interferes with one of the posts. A workaround is to find out which post that is (you have a 50% chance of guessing it right, accounting for rotating the board) and then filing away the corner of the post pointing inwards by a few millimetres.

[[File:Quartz64-audio-jack-spacer-issue.jpg]]

An alternate solution may be to place plastic spacers with a smaller outer diameter in between the acrylic bottom plate posts and the SBC board.

=== No GPU Acceleration with Debian "Bullseye" Userland ===

Debian Bullseye ships a Mesa version that is too old to contain the required patches for the RK356x SoC's GPU. You can (at your own risk) [https://wiki.debian.org/DebianTesting use the current Debian Testing version ], called "Bookworm".

== How-To ==

=== Connect Debug UART ===

The easiest way to get debug output is to connect a 3.3V 1.5mbaud capable UART adapter to the board.

To connect it, connect the ground lead to pin 6, and the RX/TX leads to pins 8 and 10 (consider swapping them if you get no output, things are often mislabelled). These pins are "UART2" in the above GPIO table.

Open a serial terminal at 1500000 bauds, e.g.

$ picocom -b 1500000 /dev/ttyUSB0

=== Disable Heartbeat LED (Linux) ===

The flashing LED is called the "heartbeat LED", it blinks in a heart rhythm like fashion once the kernel is running. To disable it, you can run

# echo none > /sys/class/leds/user-led/trigger

On a system with systemd, you can do this as soon as the system is ready to be logged in with a systemd unit like this:

[Unit]
Description=Turn off heartbeat LED
Wants=multi-user.target
After=multi-user.target

[Install]
WantedBy=multi-user.target

[Service]
Type=simple
ExecStart=sh -c 'echo none > /sys/class/leds/user-led/trigger'

Place it in <tt>/etc/systemd/system/user-led.service</tt>, and run

# systemctl daemon-reload
# systemctl enable user-led.service

Upon rebooting, you will now notice that the heartbeat LED will blink during boot-up, but stops blinking as soon as the multi-user target is reached (i.e. the user can log in).

[[Category:Quartz64]]