PINE64 - User contributions [en]

Quartz64

2022-06-07T10:02:54Z

Bullet64: /* GPIO Pins (Quartz64 Model B) */

[[File:Quartz64modelb.png|400px|thumb|right|The Quartz64 Model B]]

The '''Quartz64''' is the most recent Single Board Computer offering from PINE64, with Model A initially released in June of 2021 and Model B in May of 2022. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software releases ==

{{warning|Software for the Quartz64 is still early in development, and therefore currently lacks features such as the ability to produce video output. You are strongly encouraged to procure a 3.3V UART serial adapter capable of running at 1.5 mbauds, such as [https://pine64.com/product/serial-console-woodpecker-edition/ the woodpecker] if you want to use a Quartz64 at this stage.}}

=== Manjaro ARM ===
[[File:Manjaro.png|right|100px]]

Manjaro ARM is a user friendly rolling release distribution, based on Arch Linux ARM.

==== Manjaro ARM with no desktop ====

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
Note, manjaro currently ships with the linux-rc kernel. Currently (and temporarily/as of writing), usb3, pcie and sata devices will not be found unless you swap to the linux-quartz64 kernel <code>pacman -S linux-quartz64</code>.
* [https://github.com/manjaro-arm/quartz64-a-images/releases Images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

==== Manjaro ARM with desktop environment ====

Since '''Dev 20211117''' with hdmi output (linux-rc)

* Gnome
* KDE Plasma
* Mate
* Sway
* XFCE

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

=== pgwipeout's Quartz64 CI ===

pgwipeout provides continuously rebuilt set of images for Quartz64 devices which includes a Debian installer and a buildroot rescue environment. It is aimed at advanced users who generally know their way around a Linux system, and as a baseline for whether something is working or not. Works on both SD cards and eMMC, uses pgwipeout's patched kernel. Kernels aren't auto-updated on the installed system, so the user manually has to do this by mounting the actual correct boot partition.

'''Download:''' https://gitlab.com/pgwipeout/quartz64_ci/-/pipelines (Click the three dots on the right, download the merge-job archive.)

For Quartz64 Model A, flash <tt>rk3566-quartz64-a.dtb.img.xz</tt>. On Linux, you can for example do this as follows, assuming your target device is <tt>/dev/sdX</tt>:

sudo -i; xzcat /path/to/rk3566-quartz64-a.dtb.img.xz > /dev/sdX

For Quartz64 Model B, use <tt>rk3566-quartz64-b.dtb.img.xz</tt> instead.

For line by line instructions to boot Quartz64 CI on a microSD card and use it to install Debian onto an eMMC follow these instructions https://wiki.pine64.org/wiki/Installing_Debian_on_the_Quartz64

=== Arch Linux ARM (Unofficial) ===

See [[Installing Arch Linux ARM On The Quartz64]] for detailed instructions.

=== Tianocore EDK II port by jmcneill ===

This (as of 2021-12-30) is a work in progress to enable UEFI enabled systems, and is able to bring up SD, eMMC, USB, PCIe with SATA and NVMe, HDMI, thermal sensors, TRNG, as well as general Cortex A-55 features. Known to work with NetBSD -current, and the ESXi Arm fling version 1.8.

* [https://github.com/jaredmcneill/quartz64_uefi jmcneill's Quartz64 UEFI Github]

The sdcard image should be written to an microSD card and installed. Currently, using this card also for the OS may be problematic.

=== NetBSD ===

NetBSD relies upon the UEFI support in Tianocore. Before NetBSD 10 is released, the latest version of NetBSD-current should be used:

* [http://nycdn.netbsd.org/pub/NetBSD-daily/HEAD/ NetBSD daily builds top level] from inside here, navigate to a date, and inside the images/ subdirectory are installable images. Use the one called "NetBSD-<version>-evbarm-aarch64-install.img.gz". This image can be written to a supported device, such as the eMMC interface, any USB storage device, NVMe, and PCIe AHCI SATA are all supported with builds after 2022-01-15.

* Currently this can not be shared with the EDK2 port, ie, microSD for EDK2 and some other media for NetBSD.

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support
* [https://www.cnx-software.com/2020/12/01/rockchip-rk3568-processor-to-power-edge-computing-and-nvr-applications 22nm process, believed to be FD-SOI]

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB (SOQuartz only), 4GB, 8GB LPDDR4.

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB
** Model A: 2 USB 2.0 host ports, 1 USB 2.0 OTG port, 1 USB 3.0 host port
** Model B: 1 USB 2.0 host port, 1 USB 2.0 OTG port, 1 USB 3.0 host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 16GB up to 128GB

==== eMMC Speeds ====

On a 64 GB eMMC module:

$ sudo hdparm -tT /dev/mmcblk1

/dev/mmcblk1:
Timing cached reads: 2368 MB in 2.00 seconds = 1184.46 MB/sec
Timing buffered disk reads: 452 MB in 3.01 seconds = 149.98 MB/sec

=== Expansion Ports ===
* HDMI
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints
** On Model A, the slot provides 10W of power for the 3.3V supply and however much power your 12V input power supply provides on the 12V supply

The PCIe implementation on the RK3566 is much more compatible with a wide range of devices compared to the one on the RK3399 used on the ROCKPro64. This means a lot more devices should work (excluding dGPUs due to a lack of cache snooping ability).

==== Combo PHYs ====

[[File:rk3566 phy.png]]

Several of the I/O options on the RK3566 used in the Quartz64 are using the same I/O lines, meaning that they cannot be used at the same time. The above diagram illustrates how they are connected.

In particular, USB 3.0 and the SATA connector on the board are mutually exclusive, and the PCI-e 2.0 lane can be reconfigured into a second SATA port, though an adapter cable needs to be fashioned for this to be useful.

=== GPIO Pins (Quartz64 Model A) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin no.
! scope="col" | Pin no.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX a
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX a
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT c
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

====Notes====
<ol style="list-style-type:lower-alpha">
<li>can be a PWM pin</li>
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
<li>low-pass filtered with cutoff of 220 MHz</li>
</ol>

Source: Page 28 of [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf the board schematics].

=== GPIO Pins (Quartz64 Model B) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin no.
! scope="col" | Pin no.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 1
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| GPIO1_A0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| GPIO1_A1_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_C4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX
|-
| style="text-align:right;"| GPIO3_A1_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| GPIO3_A3_3V3
|-
| style="text-align:right;"| GPIO3_A2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GPIO3_B1_3V3
|-
| style="text-align:right;"| 3.3V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 17
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| GPIO3_B2_3V3
|-
| style="text-align:right;"| GPIO4_C3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO4_C5_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 21
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 22
| style="text-align:left;"| GPIO3_C1_3V3
|-
| style="text-align:right;"| GPIO4_C2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 23
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 24
| style="text-align:left;"| GPIO4_C6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 25
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 26
| style="text-align:left;"| GPIO4_D1_3V3
|-
| style="text-align:right;"| I2C4_SDA_M0
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 27
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 28
| style="text-align:left;"| I2C4_SCL_M0
|-
| style="text-align:right;"| GPIO3_B3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 29
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 30
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 31
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 32
| style="text-align:left;"| GPIO3_C2_3V3
|-
| style="text-align:right;"| GPIO3_C3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 33
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 34
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 35
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 36
| style="text-align:left;"| GPIO3_A7_3V3
|-
| style="text-align:right;"| GPIO1_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 37
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 38
| style="text-align:left;"| GPIO3_A6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 39
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 40
| style="text-align:left;"| GPIO3_A5_3V3
|}

Source: Page 24 of [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf the board schematics].

== Quartz64 Board Information, Schematics, and Certifications ==

=== Model "A" ===
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Quartz64 Model "A" SBC Schematic ver 2.0 20210427 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V2.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Certifications:
** Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary. However, PINE64 still submit the SBC for FCC and CE certification and obtain the certificates to proof that SBC board is capable on passing the testing. Please note a final commercial product needs to performs its owns testing and obtains its owns certificates.
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20CE%20certification-S21051101701001.pdf Quartz64 model-A CE Certificate]
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20FCC%20certification-S21051101702001.pdf Quartz64 model-A FCC Certificate]

=== Model "B" ===

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID center-positive Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf Quartz64 Model "B" SBC Schematic ver 1.3 20220124 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_PCB_Components_Placement-V1.2_20211014.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]
* Please note that v1.2 and V1.3 schematic and component placement are identical, just some component value changed.

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK817%20datasheet%20V1.01.pdf Rockchip RK817 ver 1.01 datasheet for Quartz64 model A]
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for Quartz64 model B and SOQuartz]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
** [https://files.pine64.org/doc/datasheet/PineNote/TI%20PMU-TPS651851.pdf TPS65185x PMIC for E-Ink Enabled Electronic Paper Display Datasheet]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

=== Android 11 Production Test Build for Quartz64 model A SBC ===

==== Android 11 Stock Image [eMMC Boot] using DD method [20210604] ====
* DD image to eMMC module using USB adapter for eMMC module and boot. Highly recommend using [https://etcher.io/ Etcher]
* This is test build that used during product testing
* Please allow 3-5 minutes boot up time on first time for initialization
* DD image for 8GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-8GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): e4365753e584d9fce1b8f10f095eede6
*** File Size: 819MB
* DD image for 16GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-16GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 491c5f7744b0ca0b74ae76e607051836
*** File Size: 1.10GB
* DD image for 32GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-32GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 47a6f0cdac8bad06cb920743849a8894
*** File Size: 846MB
* DD image for 64GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-64GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 4e2fed6f5db0d55afdc8a142fc0c4fe1
*** File Size: 884MB

==== Android 11 Production Test Build for Quartz64 model A SBC [eMMC Boot] using ROCKChip tools method [20210604] ====
* Please unzip first and then using [https://files.pine64.org/os/Quartz64//android/RKDevTool_Release_v2.84.zip Rockchip Android tool ver 2.84] to flash in
* For Windows OS environment, please install the [https://files.pine64.org/os/Quartz64/android/DriverAssitant_v5.1.1.zip DriverAssistant v5.11] driver first
* This is test build that used during product testing
* The OTG port located at top USB 2.0 port on top of USB 3.0 port, needs USB type A to type A cable.
* Please allow 3-5 minutes boot up time on first time for initialization
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_20210604_stock_android11_emmcboot.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 800f867fdd0d1b2bd7822c156b6067e3
*** File Size: 812MB

=== Android 11 eink SDK for Quartz64 model A SBC ===
* The is the Android SDK build for 10.3" eink panel on Quartz64 model A SBC.
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_eink.android11_SDK.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 293a550584298de4fb95ceae18103672
** File Size: 72.88GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Enclosures ==

(Please expand this section with more cases known to work.)

=== Model "A" ===

All enclosures that fit the ROCKPro64 should fit the Quartz64 Model "A", as the I/O has been laid out the same on purpose.

* [["Model A" Acrylic Open Enclosure]] - but see the troubleshooting section below.
* [[ROCKPro64 ABS Enclosure]]
* [[Quartz64PremiumAluminiumCase|RockPro64 Premium Aluminium Case]]
* [[ROCKPro64#3D_printable_ITX_mounting_brackets]] (Not an enclosure but allows to mount the board in an ATX/ITX case)

=== Model "B" ===

* [["Model B" Acrylic Open Enclosure]]
* the ROCK64 aluminium enclosure '''does not''' work, as the DC input jack is placed differently

== Troubleshooting ==

=== Stability/Boot Issues With Missing Battery Shunt ===

If there is no battery plugged into the board, the jumper labelled "ON/OFF_BATT" must be in place. If this is set wrong, stability issues such as failures to boot will occur.

=== No Ethernet Connectivity ===

Make sure the kernel is built with <code>CONFIG_MOTORCOMM_PHY</code> set to <code>y</code>. Building it as a module (<code>m</code>) and then relying on module auto-loading is unlikely to work, because if the generic PHY driver is built in it will bind to the PHY first, unless you include the motorcomm module in your initramfs.

=== "Model A" Acrylic Case Doesn't Fit ===

The Quartz64 does not really fit onto the bottom plate of the [["Model A" Acrylic Open Enclosure]]. This is because the "Mic" connector at the bottom of the board interferes with one of the posts. A workaround is to find out which post that is (you have a 50% chance of guessing it right, accounting for rotating the board) and then filing away the corner of the post pointing inwards by a few millimetres.

[[File:Quartz64-audio-jack-spacer-issue.jpg]]

An alternate solution may be to place plastic spacers with a smaller outer diameter in between the acrylic bottom plate posts and the SBC board.

=== No GPU Acceleration with Debian "Bullseye" Userland ===

Debian Bullseye ships a Mesa version that is too old to contain the required patches for the RK356x SoC's GPU. You can (at your own risk) [https://wiki.debian.org/DebianTesting use the current Debian Testing version ], called "Bookworm".

[[Category:Quartz64]]

Quartz64

2022-06-07T10:02:38Z

Bullet64: /* GPIO Pins (Quartz64 Model A) */

[[File:Quartz64modelb.png|400px|thumb|right|The Quartz64 Model B]]

The '''Quartz64''' is the most recent Single Board Computer offering from PINE64, with Model A initially released in June of 2021 and Model B in May of 2022. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software releases ==

{{warning|Software for the Quartz64 is still early in development, and therefore currently lacks features such as the ability to produce video output. You are strongly encouraged to procure a 3.3V UART serial adapter capable of running at 1.5 mbauds, such as [https://pine64.com/product/serial-console-woodpecker-edition/ the woodpecker] if you want to use a Quartz64 at this stage.}}

=== Manjaro ARM ===
[[File:Manjaro.png|right|100px]]

Manjaro ARM is a user friendly rolling release distribution, based on Arch Linux ARM.

==== Manjaro ARM with no desktop ====

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
Note, manjaro currently ships with the linux-rc kernel. Currently (and temporarily/as of writing), usb3, pcie and sata devices will not be found unless you swap to the linux-quartz64 kernel <code>pacman -S linux-quartz64</code>.
* [https://github.com/manjaro-arm/quartz64-a-images/releases Images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

==== Manjaro ARM with desktop environment ====

Since '''Dev 20211117''' with hdmi output (linux-rc)

* Gnome
* KDE Plasma
* Mate
* Sway
* XFCE

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

=== pgwipeout's Quartz64 CI ===

pgwipeout provides continuously rebuilt set of images for Quartz64 devices which includes a Debian installer and a buildroot rescue environment. It is aimed at advanced users who generally know their way around a Linux system, and as a baseline for whether something is working or not. Works on both SD cards and eMMC, uses pgwipeout's patched kernel. Kernels aren't auto-updated on the installed system, so the user manually has to do this by mounting the actual correct boot partition.

'''Download:''' https://gitlab.com/pgwipeout/quartz64_ci/-/pipelines (Click the three dots on the right, download the merge-job archive.)

For Quartz64 Model A, flash <tt>rk3566-quartz64-a.dtb.img.xz</tt>. On Linux, you can for example do this as follows, assuming your target device is <tt>/dev/sdX</tt>:

sudo -i; xzcat /path/to/rk3566-quartz64-a.dtb.img.xz > /dev/sdX

For Quartz64 Model B, use <tt>rk3566-quartz64-b.dtb.img.xz</tt> instead.

For line by line instructions to boot Quartz64 CI on a microSD card and use it to install Debian onto an eMMC follow these instructions https://wiki.pine64.org/wiki/Installing_Debian_on_the_Quartz64

=== Arch Linux ARM (Unofficial) ===

See [[Installing Arch Linux ARM On The Quartz64]] for detailed instructions.

=== Tianocore EDK II port by jmcneill ===

This (as of 2021-12-30) is a work in progress to enable UEFI enabled systems, and is able to bring up SD, eMMC, USB, PCIe with SATA and NVMe, HDMI, thermal sensors, TRNG, as well as general Cortex A-55 features. Known to work with NetBSD -current, and the ESXi Arm fling version 1.8.

* [https://github.com/jaredmcneill/quartz64_uefi jmcneill's Quartz64 UEFI Github]

The sdcard image should be written to an microSD card and installed. Currently, using this card also for the OS may be problematic.

=== NetBSD ===

NetBSD relies upon the UEFI support in Tianocore. Before NetBSD 10 is released, the latest version of NetBSD-current should be used:

* [http://nycdn.netbsd.org/pub/NetBSD-daily/HEAD/ NetBSD daily builds top level] from inside here, navigate to a date, and inside the images/ subdirectory are installable images. Use the one called "NetBSD-<version>-evbarm-aarch64-install.img.gz". This image can be written to a supported device, such as the eMMC interface, any USB storage device, NVMe, and PCIe AHCI SATA are all supported with builds after 2022-01-15.

* Currently this can not be shared with the EDK2 port, ie, microSD for EDK2 and some other media for NetBSD.

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support
* [https://www.cnx-software.com/2020/12/01/rockchip-rk3568-processor-to-power-edge-computing-and-nvr-applications 22nm process, believed to be FD-SOI]

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB (SOQuartz only), 4GB, 8GB LPDDR4.

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB
** Model A: 2 USB 2.0 host ports, 1 USB 2.0 OTG port, 1 USB 3.0 host port
** Model B: 1 USB 2.0 host port, 1 USB 2.0 OTG port, 1 USB 3.0 host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 16GB up to 128GB

==== eMMC Speeds ====

On a 64 GB eMMC module:

$ sudo hdparm -tT /dev/mmcblk1

/dev/mmcblk1:
Timing cached reads: 2368 MB in 2.00 seconds = 1184.46 MB/sec
Timing buffered disk reads: 452 MB in 3.01 seconds = 149.98 MB/sec

=== Expansion Ports ===
* HDMI
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints
** On Model A, the slot provides 10W of power for the 3.3V supply and however much power your 12V input power supply provides on the 12V supply

The PCIe implementation on the RK3566 is much more compatible with a wide range of devices compared to the one on the RK3399 used on the ROCKPro64. This means a lot more devices should work (excluding dGPUs due to a lack of cache snooping ability).

==== Combo PHYs ====

[[File:rk3566 phy.png]]

Several of the I/O options on the RK3566 used in the Quartz64 are using the same I/O lines, meaning that they cannot be used at the same time. The above diagram illustrates how they are connected.

In particular, USB 3.0 and the SATA connector on the board are mutually exclusive, and the PCI-e 2.0 lane can be reconfigured into a second SATA port, though an adapter cable needs to be fashioned for this to be useful.

=== GPIO Pins (Quartz64 Model A) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin no.
! scope="col" | Pin no.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX a
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX a
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT c
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

====Notes====
<ol style="list-style-type:lower-alpha">
<li>can be a PWM pin</li>
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
<li>low-pass filtered with cutoff of 220 MHz</li>
</ol>

Source: Page 28 of [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf the board schematics].

=== GPIO Pins (Quartz64 Model B) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 1
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| GPIO1_A0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| GPIO1_A1_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_C4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX
|-
| style="text-align:right;"| GPIO3_A1_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| GPIO3_A3_3V3
|-
| style="text-align:right;"| GPIO3_A2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GPIO3_B1_3V3
|-
| style="text-align:right;"| 3.3V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 17
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| GPIO3_B2_3V3
|-
| style="text-align:right;"| GPIO4_C3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO4_C5_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 21
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 22
| style="text-align:left;"| GPIO3_C1_3V3
|-
| style="text-align:right;"| GPIO4_C2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 23
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 24
| style="text-align:left;"| GPIO4_C6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 25
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 26
| style="text-align:left;"| GPIO4_D1_3V3
|-
| style="text-align:right;"| I2C4_SDA_M0
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 27
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 28
| style="text-align:left;"| I2C4_SCL_M0
|-
| style="text-align:right;"| GPIO3_B3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 29
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 30
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 31
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 32
| style="text-align:left;"| GPIO3_C2_3V3
|-
| style="text-align:right;"| GPIO3_C3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 33
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 34
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 35
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 36
| style="text-align:left;"| GPIO3_A7_3V3
|-
| style="text-align:right;"| GPIO1_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 37
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 38
| style="text-align:left;"| GPIO3_A6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 39
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 40
| style="text-align:left;"| GPIO3_A5_3V3
|}

Source: Page 24 of [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf the board schematics].

== Quartz64 Board Information, Schematics, and Certifications ==

=== Model "A" ===
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Quartz64 Model "A" SBC Schematic ver 2.0 20210427 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V2.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Certifications:
** Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary. However, PINE64 still submit the SBC for FCC and CE certification and obtain the certificates to proof that SBC board is capable on passing the testing. Please note a final commercial product needs to performs its owns testing and obtains its owns certificates.
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20CE%20certification-S21051101701001.pdf Quartz64 model-A CE Certificate]
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20FCC%20certification-S21051101702001.pdf Quartz64 model-A FCC Certificate]

=== Model "B" ===

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID center-positive Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf Quartz64 Model "B" SBC Schematic ver 1.3 20220124 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_PCB_Components_Placement-V1.2_20211014.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]
* Please note that v1.2 and V1.3 schematic and component placement are identical, just some component value changed.

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK817%20datasheet%20V1.01.pdf Rockchip RK817 ver 1.01 datasheet for Quartz64 model A]
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for Quartz64 model B and SOQuartz]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
** [https://files.pine64.org/doc/datasheet/PineNote/TI%20PMU-TPS651851.pdf TPS65185x PMIC for E-Ink Enabled Electronic Paper Display Datasheet]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

=== Android 11 Production Test Build for Quartz64 model A SBC ===

==== Android 11 Stock Image [eMMC Boot] using DD method [20210604] ====
* DD image to eMMC module using USB adapter for eMMC module and boot. Highly recommend using [https://etcher.io/ Etcher]
* This is test build that used during product testing
* Please allow 3-5 minutes boot up time on first time for initialization
* DD image for 8GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-8GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): e4365753e584d9fce1b8f10f095eede6
*** File Size: 819MB
* DD image for 16GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-16GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 491c5f7744b0ca0b74ae76e607051836
*** File Size: 1.10GB
* DD image for 32GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-32GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 47a6f0cdac8bad06cb920743849a8894
*** File Size: 846MB
* DD image for 64GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-64GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 4e2fed6f5db0d55afdc8a142fc0c4fe1
*** File Size: 884MB

==== Android 11 Production Test Build for Quartz64 model A SBC [eMMC Boot] using ROCKChip tools method [20210604] ====
* Please unzip first and then using [https://files.pine64.org/os/Quartz64//android/RKDevTool_Release_v2.84.zip Rockchip Android tool ver 2.84] to flash in
* For Windows OS environment, please install the [https://files.pine64.org/os/Quartz64/android/DriverAssitant_v5.1.1.zip DriverAssistant v5.11] driver first
* This is test build that used during product testing
* The OTG port located at top USB 2.0 port on top of USB 3.0 port, needs USB type A to type A cable.
* Please allow 3-5 minutes boot up time on first time for initialization
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_20210604_stock_android11_emmcboot.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 800f867fdd0d1b2bd7822c156b6067e3
*** File Size: 812MB

=== Android 11 eink SDK for Quartz64 model A SBC ===
* The is the Android SDK build for 10.3" eink panel on Quartz64 model A SBC.
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_eink.android11_SDK.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 293a550584298de4fb95ceae18103672
** File Size: 72.88GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Enclosures ==

(Please expand this section with more cases known to work.)

=== Model "A" ===

All enclosures that fit the ROCKPro64 should fit the Quartz64 Model "A", as the I/O has been laid out the same on purpose.

* [["Model A" Acrylic Open Enclosure]] - but see the troubleshooting section below.
* [[ROCKPro64 ABS Enclosure]]
* [[Quartz64PremiumAluminiumCase|RockPro64 Premium Aluminium Case]]
* [[ROCKPro64#3D_printable_ITX_mounting_brackets]] (Not an enclosure but allows to mount the board in an ATX/ITX case)

=== Model "B" ===

* [["Model B" Acrylic Open Enclosure]]
* the ROCK64 aluminium enclosure '''does not''' work, as the DC input jack is placed differently

== Troubleshooting ==

=== Stability/Boot Issues With Missing Battery Shunt ===

If there is no battery plugged into the board, the jumper labelled "ON/OFF_BATT" must be in place. If this is set wrong, stability issues such as failures to boot will occur.

=== No Ethernet Connectivity ===

Make sure the kernel is built with <code>CONFIG_MOTORCOMM_PHY</code> set to <code>y</code>. Building it as a module (<code>m</code>) and then relying on module auto-loading is unlikely to work, because if the generic PHY driver is built in it will bind to the PHY first, unless you include the motorcomm module in your initramfs.

=== "Model A" Acrylic Case Doesn't Fit ===

The Quartz64 does not really fit onto the bottom plate of the [["Model A" Acrylic Open Enclosure]]. This is because the "Mic" connector at the bottom of the board interferes with one of the posts. A workaround is to find out which post that is (you have a 50% chance of guessing it right, accounting for rotating the board) and then filing away the corner of the post pointing inwards by a few millimetres.

[[File:Quartz64-audio-jack-spacer-issue.jpg]]

An alternate solution may be to place plastic spacers with a smaller outer diameter in between the acrylic bottom plate posts and the SBC board.

=== No GPU Acceleration with Debian "Bullseye" Userland ===

Debian Bullseye ships a Mesa version that is too old to contain the required patches for the RK356x SoC's GPU. You can (at your own risk) [https://wiki.debian.org/DebianTesting use the current Debian Testing version ], called "Bookworm".

[[Category:Quartz64]]

Quartz64

2022-06-07T09:47:14Z

Bullet64: /* GPIO Pins (Quartz64 Model B) */

[[File:Quartz64modelb.png|400px|thumb|right|The Quartz64 Model B]]

The '''Quartz64''' is the most recent Single Board Computer offering from PINE64, with Model A initially released in June of 2021 and Model B in May of 2022. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software releases ==

{{warning|Software for the Quartz64 is still early in development, and therefore currently lacks features such as the ability to produce video output. You are strongly encouraged to procure a 3.3V UART serial adapter capable of running at 1.5 mbauds, such as [https://pine64.com/product/serial-console-woodpecker-edition/ the woodpecker] if you want to use a Quartz64 at this stage.}}

=== Manjaro ARM ===
[[File:Manjaro.png|right|100px]]

Manjaro ARM is a user friendly rolling release distribution, based on Arch Linux ARM.

==== Manjaro ARM with no desktop ====

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
Note, manjaro currently ships with the linux-rc kernel. Currently (and temporarily/as of writing), usb3, pcie and sata devices will not be found unless you swap to the linux-quartz64 kernel <code>pacman -S linux-quartz64</code>.
* [https://github.com/manjaro-arm/quartz64-a-images/releases Images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

==== Manjaro ARM with desktop environment ====

Since '''Dev 20211117''' with hdmi output (linux-rc)

* Gnome
* KDE Plasma
* Mate
* Sway
* XFCE

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

=== pgwipeout's Quartz64 CI ===

pgwipeout provides continuously rebuilt set of images for Quartz64 devices which includes a Debian installer and a buildroot rescue environment. It is aimed at advanced users who generally know their way around a Linux system, and as a baseline for whether something is working or not. Works on both SD cards and eMMC, uses pgwipeout's patched kernel. Kernels aren't auto-updated on the installed system, so the user manually has to do this by mounting the actual correct boot partition.

'''Download:''' https://gitlab.com/pgwipeout/quartz64_ci/-/pipelines (Click the three dots on the right, download the merge-job archive.)

For Quartz64 Model A, flash <tt>rk3566-quartz64-a.dtb.img.xz</tt>. On Linux, you can for example do this as follows, assuming your target device is <tt>/dev/sdX</tt>:

sudo -i; xzcat /path/to/rk3566-quartz64-a.dtb.img.xz > /dev/sdX

For Quartz64 Model B, use <tt>rk3566-quartz64-b.dtb.img.xz</tt> instead.

For line by line instructions to boot Quartz64 CI on a microSD card and use it to install Debian onto an eMMC follow these instructions https://wiki.pine64.org/wiki/Installing_Debian_on_the_Quartz64

=== Arch Linux ARM (Unofficial) ===

See [[Installing Arch Linux ARM On The Quartz64]] for detailed instructions.

=== Tianocore EDK II port by jmcneill ===

This (as of 2021-12-30) is a work in progress to enable UEFI enabled systems, and is able to bring up SD, eMMC, USB, PCIe with SATA and NVMe, HDMI, thermal sensors, TRNG, as well as general Cortex A-55 features. Known to work with NetBSD -current, and the ESXi Arm fling version 1.8.

* [https://github.com/jaredmcneill/quartz64_uefi jmcneill's Quartz64 UEFI Github]

The sdcard image should be written to an microSD card and installed. Currently, using this card also for the OS may be problematic.

=== NetBSD ===

NetBSD relies upon the UEFI support in Tianocore. Before NetBSD 10 is released, the latest version of NetBSD-current should be used:

* [http://nycdn.netbsd.org/pub/NetBSD-daily/HEAD/ NetBSD daily builds top level] from inside here, navigate to a date, and inside the images/ subdirectory are installable images. Use the one called "NetBSD-<version>-evbarm-aarch64-install.img.gz". This image can be written to a supported device, such as the eMMC interface, any USB storage device, NVMe, and PCIe AHCI SATA are all supported with builds after 2022-01-15.

* Currently this can not be shared with the EDK2 port, ie, microSD for EDK2 and some other media for NetBSD.

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support
* [https://www.cnx-software.com/2020/12/01/rockchip-rk3568-processor-to-power-edge-computing-and-nvr-applications 22nm process, believed to be FD-SOI]

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB (SOQuartz only), 4GB, 8GB LPDDR4.

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB
** Model A: 2 USB 2.0 host ports, 1 USB 2.0 OTG port, 1 USB 3.0 host port
** Model B: 1 USB 2.0 host port, 1 USB 2.0 OTG port, 1 USB 3.0 host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 16GB up to 128GB

==== eMMC Speeds ====

On a 64 GB eMMC module:

$ sudo hdparm -tT /dev/mmcblk1

/dev/mmcblk1:
Timing cached reads: 2368 MB in 2.00 seconds = 1184.46 MB/sec
Timing buffered disk reads: 452 MB in 3.01 seconds = 149.98 MB/sec

=== Expansion Ports ===
* HDMI
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints
** On Model A, the slot provides 10W of power for the 3.3V supply and however much power your 12V input power supply provides on the 12V supply

The PCIe implementation on the RK3566 is much more compatible with a wide range of devices compared to the one on the RK3399 used on the ROCKPro64. This means a lot more devices should work (excluding dGPUs due to a lack of cache snooping ability).

==== Combo PHYs ====

[[File:rk3566 phy.png]]

Several of the I/O options on the RK3566 used in the Quartz64 are using the same I/O lines, meaning that they cannot be used at the same time. The above diagram illustrates how they are connected.

In particular, USB 3.0 and the SATA connector on the board are mutually exclusive, and the PCI-e 2.0 lane can be reconfigured into a second SATA port, though an adapter cable needs to be fashioned for this to be useful.

=== GPIO Pins (Quartz64 Model A) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX a
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX a
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT c
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

====Notes====
<ol style="list-style-type:lower-alpha">
<li>can be a PWM pin</li>
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
<li>low-pass filtered with cutoff of 220 MHz</li>
</ol>

Source: Page 28 of [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf the board schematics].

=== GPIO Pins (Quartz64 Model B) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 1
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| GPIO1_A0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| GPIO1_A1_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_C4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX
|-
| style="text-align:right;"| GPIO3_A1_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| GPIO3_A3_3V3
|-
| style="text-align:right;"| GPIO3_A2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GPIO3_B1_3V3
|-
| style="text-align:right;"| 3.3V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 17
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| GPIO3_B2_3V3
|-
| style="text-align:right;"| GPIO4_C3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO4_C5_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 21
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 22
| style="text-align:left;"| GPIO3_C1_3V3
|-
| style="text-align:right;"| GPIO4_C2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 23
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 24
| style="text-align:left;"| GPIO4_C6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 25
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 26
| style="text-align:left;"| GPIO4_D1_3V3
|-
| style="text-align:right;"| I2C4_SDA_M0
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 27
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 28
| style="text-align:left;"| I2C4_SCL_M0
|-
| style="text-align:right;"| GPIO3_B3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 29
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 30
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 31
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 32
| style="text-align:left;"| GPIO3_C2_3V3
|-
| style="text-align:right;"| GPIO3_C3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 33
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 34
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 35
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 36
| style="text-align:left;"| GPIO3_A7_3V3
|-
| style="text-align:right;"| GPIO1_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 37
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 38
| style="text-align:left;"| GPIO3_A6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 39
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 40
| style="text-align:left;"| GPIO3_A5_3V3
|}

Source: Page 24 of [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf the board schematics].

== Quartz64 Board Information, Schematics, and Certifications ==

=== Model "A" ===
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Quartz64 Model "A" SBC Schematic ver 2.0 20210427 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V2.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Certifications:
** Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary. However, PINE64 still submit the SBC for FCC and CE certification and obtain the certificates to proof that SBC board is capable on passing the testing. Please note a final commercial product needs to performs its owns testing and obtains its owns certificates.
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20CE%20certification-S21051101701001.pdf Quartz64 model-A CE Certificate]
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20FCC%20certification-S21051101702001.pdf Quartz64 model-A FCC Certificate]

=== Model "B" ===

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID center-positive Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf Quartz64 Model "B" SBC Schematic ver 1.3 20220124 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_PCB_Components_Placement-V1.2_20211014.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]
* Please note that v1.2 and V1.3 schematic and component placement are identical, just some component value changed.

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK817%20datasheet%20V1.01.pdf Rockchip RK817 ver 1.01 datasheet for Quartz64 model A]
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for Quartz64 model B and SOQuartz]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
** [https://files.pine64.org/doc/datasheet/PineNote/TI%20PMU-TPS651851.pdf TPS65185x PMIC for E-Ink Enabled Electronic Paper Display Datasheet]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

=== Android 11 Production Test Build for Quartz64 model A SBC ===

==== Android 11 Stock Image [eMMC Boot] using DD method [20210604] ====
* DD image to eMMC module using USB adapter for eMMC module and boot. Highly recommend using [https://etcher.io/ Etcher]
* This is test build that used during product testing
* Please allow 3-5 minutes boot up time on first time for initialization
* DD image for 8GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-8GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): e4365753e584d9fce1b8f10f095eede6
*** File Size: 819MB
* DD image for 16GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-16GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 491c5f7744b0ca0b74ae76e607051836
*** File Size: 1.10GB
* DD image for 32GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-32GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 47a6f0cdac8bad06cb920743849a8894
*** File Size: 846MB
* DD image for 64GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-64GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 4e2fed6f5db0d55afdc8a142fc0c4fe1
*** File Size: 884MB

==== Android 11 Production Test Build for Quartz64 model A SBC [eMMC Boot] using ROCKChip tools method [20210604] ====
* Please unzip first and then using [https://files.pine64.org/os/Quartz64//android/RKDevTool_Release_v2.84.zip Rockchip Android tool ver 2.84] to flash in
* For Windows OS environment, please install the [https://files.pine64.org/os/Quartz64/android/DriverAssitant_v5.1.1.zip DriverAssistant v5.11] driver first
* This is test build that used during product testing
* The OTG port located at top USB 2.0 port on top of USB 3.0 port, needs USB type A to type A cable.
* Please allow 3-5 minutes boot up time on first time for initialization
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_20210604_stock_android11_emmcboot.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 800f867fdd0d1b2bd7822c156b6067e3
*** File Size: 812MB

=== Android 11 eink SDK for Quartz64 model A SBC ===
* The is the Android SDK build for 10.3" eink panel on Quartz64 model A SBC.
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_eink.android11_SDK.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 293a550584298de4fb95ceae18103672
** File Size: 72.88GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Enclosures ==

(Please expand this section with more cases known to work.)

=== Model "A" ===

All enclosures that fit the ROCKPro64 should fit the Quartz64 Model "A", as the I/O has been laid out the same on purpose.

* [["Model A" Acrylic Open Enclosure]] - but see the troubleshooting section below.
* [[ROCKPro64 ABS Enclosure]]
* [[Quartz64PremiumAluminiumCase|RockPro64 Premium Aluminium Case]]
* [[ROCKPro64#3D_printable_ITX_mounting_brackets]] (Not an enclosure but allows to mount the board in an ATX/ITX case)

=== Model "B" ===

* [["Model B" Acrylic Open Enclosure]]
* the ROCK64 aluminium enclosure '''does not''' work, as the DC input jack is placed differently

== Troubleshooting ==

=== Stability/Boot Issues With Missing Battery Shunt ===

If there is no battery plugged into the board, the jumper labelled "ON/OFF_BATT" must be in place. If this is set wrong, stability issues such as failures to boot will occur.

=== No Ethernet Connectivity ===

Make sure the kernel is built with <code>CONFIG_MOTORCOMM_PHY</code> set to <code>y</code>. Building it as a module (<code>m</code>) and then relying on module auto-loading is unlikely to work, because if the generic PHY driver is built in it will bind to the PHY first, unless you include the motorcomm module in your initramfs.

=== "Model A" Acrylic Case Doesn't Fit ===

The Quartz64 does not really fit onto the bottom plate of the [["Model A" Acrylic Open Enclosure]]. This is because the "Mic" connector at the bottom of the board interferes with one of the posts. A workaround is to find out which post that is (you have a 50% chance of guessing it right, accounting for rotating the board) and then filing away the corner of the post pointing inwards by a few millimetres.

[[File:Quartz64-audio-jack-spacer-issue.jpg]]

An alternate solution may be to place plastic spacers with a smaller outer diameter in between the acrylic bottom plate posts and the SBC board.

=== No GPU Acceleration with Debian "Bullseye" Userland ===

Debian Bullseye ships a Mesa version that is too old to contain the required patches for the RK356x SoC's GPU. You can (at your own risk) [https://wiki.debian.org/DebianTesting use the current Debian Testing version ], called "Bookworm".

[[Category:Quartz64]]

Quartz64

2022-06-07T09:46:02Z

Bullet64: /* GPIO Pins (Quartz64 Model B) */

[[File:Quartz64modelb.png|400px|thumb|right|The Quartz64 Model B]]

The '''Quartz64''' is the most recent Single Board Computer offering from PINE64, with Model A initially released in June of 2021 and Model B in May of 2022. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software releases ==

{{warning|Software for the Quartz64 is still early in development, and therefore currently lacks features such as the ability to produce video output. You are strongly encouraged to procure a 3.3V UART serial adapter capable of running at 1.5 mbauds, such as [https://pine64.com/product/serial-console-woodpecker-edition/ the woodpecker] if you want to use a Quartz64 at this stage.}}

=== Manjaro ARM ===
[[File:Manjaro.png|right|100px]]

Manjaro ARM is a user friendly rolling release distribution, based on Arch Linux ARM.

==== Manjaro ARM with no desktop ====

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
Note, manjaro currently ships with the linux-rc kernel. Currently (and temporarily/as of writing), usb3, pcie and sata devices will not be found unless you swap to the linux-quartz64 kernel <code>pacman -S linux-quartz64</code>.
* [https://github.com/manjaro-arm/quartz64-a-images/releases Images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

==== Manjaro ARM with desktop environment ====

Since '''Dev 20211117''' with hdmi output (linux-rc)

* Gnome
* KDE Plasma
* Mate
* Sway
* XFCE

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

=== pgwipeout's Quartz64 CI ===

pgwipeout provides continuously rebuilt set of images for Quartz64 devices which includes a Debian installer and a buildroot rescue environment. It is aimed at advanced users who generally know their way around a Linux system, and as a baseline for whether something is working or not. Works on both SD cards and eMMC, uses pgwipeout's patched kernel. Kernels aren't auto-updated on the installed system, so the user manually has to do this by mounting the actual correct boot partition.

'''Download:''' https://gitlab.com/pgwipeout/quartz64_ci/-/pipelines (Click the three dots on the right, download the merge-job archive.)

For Quartz64 Model A, flash <tt>rk3566-quartz64-a.dtb.img.xz</tt>. On Linux, you can for example do this as follows, assuming your target device is <tt>/dev/sdX</tt>:

sudo -i; xzcat /path/to/rk3566-quartz64-a.dtb.img.xz > /dev/sdX

For Quartz64 Model B, use <tt>rk3566-quartz64-b.dtb.img.xz</tt> instead.

For line by line instructions to boot Quartz64 CI on a microSD card and use it to install Debian onto an eMMC follow these instructions https://wiki.pine64.org/wiki/Installing_Debian_on_the_Quartz64

=== Arch Linux ARM (Unofficial) ===

See [[Installing Arch Linux ARM On The Quartz64]] for detailed instructions.

=== Tianocore EDK II port by jmcneill ===

This (as of 2021-12-30) is a work in progress to enable UEFI enabled systems, and is able to bring up SD, eMMC, USB, PCIe with SATA and NVMe, HDMI, thermal sensors, TRNG, as well as general Cortex A-55 features. Known to work with NetBSD -current, and the ESXi Arm fling version 1.8.

* [https://github.com/jaredmcneill/quartz64_uefi jmcneill's Quartz64 UEFI Github]

The sdcard image should be written to an microSD card and installed. Currently, using this card also for the OS may be problematic.

=== NetBSD ===

NetBSD relies upon the UEFI support in Tianocore. Before NetBSD 10 is released, the latest version of NetBSD-current should be used:

* [http://nycdn.netbsd.org/pub/NetBSD-daily/HEAD/ NetBSD daily builds top level] from inside here, navigate to a date, and inside the images/ subdirectory are installable images. Use the one called "NetBSD-<version>-evbarm-aarch64-install.img.gz". This image can be written to a supported device, such as the eMMC interface, any USB storage device, NVMe, and PCIe AHCI SATA are all supported with builds after 2022-01-15.

* Currently this can not be shared with the EDK2 port, ie, microSD for EDK2 and some other media for NetBSD.

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support
* [https://www.cnx-software.com/2020/12/01/rockchip-rk3568-processor-to-power-edge-computing-and-nvr-applications 22nm process, believed to be FD-SOI]

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB (SOQuartz only), 4GB, 8GB LPDDR4.

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB
** Model A: 2 USB 2.0 host ports, 1 USB 2.0 OTG port, 1 USB 3.0 host port
** Model B: 1 USB 2.0 host port, 1 USB 2.0 OTG port, 1 USB 3.0 host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 16GB up to 128GB

==== eMMC Speeds ====

On a 64 GB eMMC module:

$ sudo hdparm -tT /dev/mmcblk1

/dev/mmcblk1:
Timing cached reads: 2368 MB in 2.00 seconds = 1184.46 MB/sec
Timing buffered disk reads: 452 MB in 3.01 seconds = 149.98 MB/sec

=== Expansion Ports ===
* HDMI
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints
** On Model A, the slot provides 10W of power for the 3.3V supply and however much power your 12V input power supply provides on the 12V supply

The PCIe implementation on the RK3566 is much more compatible with a wide range of devices compared to the one on the RK3399 used on the ROCKPro64. This means a lot more devices should work (excluding dGPUs due to a lack of cache snooping ability).

==== Combo PHYs ====

[[File:rk3566 phy.png]]

Several of the I/O options on the RK3566 used in the Quartz64 are using the same I/O lines, meaning that they cannot be used at the same time. The above diagram illustrates how they are connected.

In particular, USB 3.0 and the SATA connector on the board are mutually exclusive, and the PCI-e 2.0 lane can be reconfigured into a second SATA port, though an adapter cable needs to be fashioned for this to be useful.

=== GPIO Pins (Quartz64 Model A) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX a
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX a
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT c
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

====Notes====
<ol style="list-style-type:lower-alpha">
<li>can be a PWM pin</li>
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
<li>low-pass filtered with cutoff of 220 MHz</li>
</ol>

Source: Page 28 of [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf the board schematics].

=== GPIO Pins (Quartz64 Model B) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 1
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| GPIO1_A0_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:red; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| GPIO1_A1_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_C4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX
|-
| style="text-align:right;"| GPIO3_A1_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| GPIO3_A3_3V3
|-
| style="text-align:right;"| GPIO3_A2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B0_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GPIO3_B1_3V3
|-
| style="text-align:right;"| 3.3V
| style="text-align:center; background-color:yellow; color:black; font-weight:bold;"| 17
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| GPIO3_B2_3V3
|-
| style="text-align:right;"| GPIO4_C3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO4_C5_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 21
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 22
| style="text-align:left;"| GPIO3_C1_3V3
|-
| style="text-align:right;"| GPIO4_C2_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 23
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 24
| style="text-align:left;"| GPIO4_C6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 25
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 26
| style="text-align:left;"| GPIO4_D1_3V3
|-
| style="text-align:right;"| I2C4_SDA_M0
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 27
| style="text-align:center; background-color:blue; color:gold; font-weight:bold;"| 28
| style="text-align:left;"| I2C4_SCL_M0
|-
| style="text-align:right;"| GPIO3_B3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 29
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 30
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 31
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 32
| style="text-align:left;"| GPIO3_C2_3V3
|-
| style="text-align:right;"| GPIO3_C3_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 33
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 34
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 35
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 36
| style="text-align:left;"| GPIO3_A7_3V3
|-
| style="text-align:right;"| GPIO1_A4_3V3
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 37
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 38
| style="text-align:left;"| GPIO3_A6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 39
| style="text-align:center; background-color:green; color:gold; font-weight:bold;"| 40
| style="text-align:left;"| GPIO3_A5_3V3
|}

Source: Page 24 of [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf the board schematics].

== Quartz64 Board Information, Schematics, and Certifications ==

=== Model "A" ===
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Quartz64 Model "A" SBC Schematic ver 2.0 20210427 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V2.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Certifications:
** Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary. However, PINE64 still submit the SBC for FCC and CE certification and obtain the certificates to proof that SBC board is capable on passing the testing. Please note a final commercial product needs to performs its owns testing and obtains its owns certificates.
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20CE%20certification-S21051101701001.pdf Quartz64 model-A CE Certificate]
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20FCC%20certification-S21051101702001.pdf Quartz64 model-A FCC Certificate]

=== Model "B" ===

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID center-positive Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf Quartz64 Model "B" SBC Schematic ver 1.3 20220124 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_PCB_Components_Placement-V1.2_20211014.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]
* Please note that v1.2 and V1.3 schematic and component placement are identical, just some component value changed.

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK817%20datasheet%20V1.01.pdf Rockchip RK817 ver 1.01 datasheet for Quartz64 model A]
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for Quartz64 model B and SOQuartz]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
** [https://files.pine64.org/doc/datasheet/PineNote/TI%20PMU-TPS651851.pdf TPS65185x PMIC for E-Ink Enabled Electronic Paper Display Datasheet]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

=== Android 11 Production Test Build for Quartz64 model A SBC ===

==== Android 11 Stock Image [eMMC Boot] using DD method [20210604] ====
* DD image to eMMC module using USB adapter for eMMC module and boot. Highly recommend using [https://etcher.io/ Etcher]
* This is test build that used during product testing
* Please allow 3-5 minutes boot up time on first time for initialization
* DD image for 8GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-8GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): e4365753e584d9fce1b8f10f095eede6
*** File Size: 819MB
* DD image for 16GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-16GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 491c5f7744b0ca0b74ae76e607051836
*** File Size: 1.10GB
* DD image for 32GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-32GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 47a6f0cdac8bad06cb920743849a8894
*** File Size: 846MB
* DD image for 64GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-64GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 4e2fed6f5db0d55afdc8a142fc0c4fe1
*** File Size: 884MB

==== Android 11 Production Test Build for Quartz64 model A SBC [eMMC Boot] using ROCKChip tools method [20210604] ====
* Please unzip first and then using [https://files.pine64.org/os/Quartz64//android/RKDevTool_Release_v2.84.zip Rockchip Android tool ver 2.84] to flash in
* For Windows OS environment, please install the [https://files.pine64.org/os/Quartz64/android/DriverAssitant_v5.1.1.zip DriverAssistant v5.11] driver first
* This is test build that used during product testing
* The OTG port located at top USB 2.0 port on top of USB 3.0 port, needs USB type A to type A cable.
* Please allow 3-5 minutes boot up time on first time for initialization
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_20210604_stock_android11_emmcboot.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 800f867fdd0d1b2bd7822c156b6067e3
*** File Size: 812MB

=== Android 11 eink SDK for Quartz64 model A SBC ===
* The is the Android SDK build for 10.3" eink panel on Quartz64 model A SBC.
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_eink.android11_SDK.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 293a550584298de4fb95ceae18103672
** File Size: 72.88GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Enclosures ==

(Please expand this section with more cases known to work.)

=== Model "A" ===

All enclosures that fit the ROCKPro64 should fit the Quartz64 Model "A", as the I/O has been laid out the same on purpose.

* [["Model A" Acrylic Open Enclosure]] - but see the troubleshooting section below.
* [[ROCKPro64 ABS Enclosure]]
* [[Quartz64PremiumAluminiumCase|RockPro64 Premium Aluminium Case]]
* [[ROCKPro64#3D_printable_ITX_mounting_brackets]] (Not an enclosure but allows to mount the board in an ATX/ITX case)

=== Model "B" ===

* [["Model B" Acrylic Open Enclosure]]
* the ROCK64 aluminium enclosure '''does not''' work, as the DC input jack is placed differently

== Troubleshooting ==

=== Stability/Boot Issues With Missing Battery Shunt ===

If there is no battery plugged into the board, the jumper labelled "ON/OFF_BATT" must be in place. If this is set wrong, stability issues such as failures to boot will occur.

=== No Ethernet Connectivity ===

Make sure the kernel is built with <code>CONFIG_MOTORCOMM_PHY</code> set to <code>y</code>. Building it as a module (<code>m</code>) and then relying on module auto-loading is unlikely to work, because if the generic PHY driver is built in it will bind to the PHY first, unless you include the motorcomm module in your initramfs.

=== "Model A" Acrylic Case Doesn't Fit ===

The Quartz64 does not really fit onto the bottom plate of the [["Model A" Acrylic Open Enclosure]]. This is because the "Mic" connector at the bottom of the board interferes with one of the posts. A workaround is to find out which post that is (you have a 50% chance of guessing it right, accounting for rotating the board) and then filing away the corner of the post pointing inwards by a few millimetres.

[[File:Quartz64-audio-jack-spacer-issue.jpg]]

An alternate solution may be to place plastic spacers with a smaller outer diameter in between the acrylic bottom plate posts and the SBC board.

=== No GPU Acceleration with Debian "Bullseye" Userland ===

Debian Bullseye ships a Mesa version that is too old to contain the required patches for the RK356x SoC's GPU. You can (at your own risk) [https://wiki.debian.org/DebianTesting use the current Debian Testing version ], called "Bookworm".

[[Category:Quartz64]]

Quartz64

2022-06-07T08:11:39Z

Bullet64: /* GPIO Pins (Quartz64 Model B) */

[[File:Quartz64modelb.png|400px|thumb|right|The Quartz64 Model B]]

The '''Quartz64''' is the most recent Single Board Computer offering from PINE64, with Model A initially released in June of 2021 and Model B in May of 2022. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software releases ==

{{warning|Software for the Quartz64 is still early in development, and therefore currently lacks features such as the ability to produce video output. You are strongly encouraged to procure a 3.3V UART serial adapter capable of running at 1.5 mbauds, such as [https://pine64.com/product/serial-console-woodpecker-edition/ the woodpecker] if you want to use a Quartz64 at this stage.}}

=== Manjaro ARM ===
[[File:Manjaro.png|right|100px]]

Manjaro ARM is a user friendly rolling release distribution, based on Arch Linux ARM.

==== Manjaro ARM with no desktop ====

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
Note, manjaro currently ships with the linux-rc kernel. Currently (and temporarily/as of writing), usb3, pcie and sata devices will not be found unless you swap to the linux-quartz64 kernel <code>pacman -S linux-quartz64</code>.
* [https://github.com/manjaro-arm/quartz64-a-images/releases Images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

==== Manjaro ARM with desktop environment ====

Since '''Dev 20211117''' with hdmi output (linux-rc)

* Gnome
* KDE Plasma
* Mate
* Sway
* XFCE

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

=== pgwipeout's Quartz64 CI ===

pgwipeout provides continuously rebuilt set of images for Quartz64 devices which includes a Debian installer and a buildroot rescue environment. It is aimed at advanced users who generally know their way around a Linux system, and as a baseline for whether something is working or not. Works on both SD cards and eMMC, uses pgwipeout's patched kernel. Kernels aren't auto-updated on the installed system, so the user manually has to do this by mounting the actual correct boot partition.

'''Download:''' https://gitlab.com/pgwipeout/quartz64_ci/-/pipelines (Click the three dots on the right, download the merge-job archive.)

For Quartz64 Model A, flash <tt>rk3566-quartz64-a.dtb.img.xz</tt>. On Linux, you can for example do this as follows, assuming your target device is <tt>/dev/sdX</tt>:

sudo -i; xzcat /path/to/rk3566-quartz64-a.dtb.img.xz > /dev/sdX

For Quartz64 Model B, use <tt>rk3566-quartz64-b.dtb.img.xz</tt> instead.

For line by line instructions to boot Quartz64 CI on a microSD card and use it to install Debian onto an eMMC follow these instructions https://wiki.pine64.org/wiki/Installing_Debian_on_the_Quartz64

=== Arch Linux ARM (Unofficial) ===

See [[Installing Arch Linux ARM On The Quartz64]] for detailed instructions.

=== Tianocore EDK II port by jmcneill ===

This (as of 2021-12-30) is a work in progress to enable UEFI enabled systems, and is able to bring up SD, eMMC, USB, PCIe with SATA and NVMe, HDMI, thermal sensors, TRNG, as well as general Cortex A-55 features. Known to work with NetBSD -current, and the ESXi Arm fling version 1.8.

* [https://github.com/jaredmcneill/quartz64_uefi jmcneill's Quartz64 UEFI Github]

The sdcard image should be written to an microSD card and installed. Currently, using this card also for the OS may be problematic.

=== NetBSD ===

NetBSD relies upon the UEFI support in Tianocore. Before NetBSD 10 is released, the latest version of NetBSD-current should be used:

* [http://nycdn.netbsd.org/pub/NetBSD-daily/HEAD/ NetBSD daily builds top level] from inside here, navigate to a date, and inside the images/ subdirectory are installable images. Use the one called "NetBSD-<version>-evbarm-aarch64-install.img.gz". This image can be written to a supported device, such as the eMMC interface, any USB storage device, NVMe, and PCIe AHCI SATA are all supported with builds after 2022-01-15.

* Currently this can not be shared with the EDK2 port, ie, microSD for EDK2 and some other media for NetBSD.

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support
* [https://www.cnx-software.com/2020/12/01/rockchip-rk3568-processor-to-power-edge-computing-and-nvr-applications 22nm process, believed to be FD-SOI]

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB (SOQuartz only), 4GB, 8GB LPDDR4.

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB
** Model A: 2 USB 2.0 host ports, 1 USB 2.0 OTG port, 1 USB 3.0 host port
** Model B: 1 USB 2.0 host port, 1 USB 2.0 OTG port, 1 USB 3.0 host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 16GB up to 128GB

==== eMMC Speeds ====

On a 64 GB eMMC module:

$ sudo hdparm -tT /dev/mmcblk1

/dev/mmcblk1:
Timing cached reads: 2368 MB in 2.00 seconds = 1184.46 MB/sec
Timing buffered disk reads: 452 MB in 3.01 seconds = 149.98 MB/sec

=== Expansion Ports ===
* HDMI
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints
** On Model A, the slot provides 10W of power for the 3.3V supply and however much power your 12V input power supply provides on the 12V supply

The PCIe implementation on the RK3566 is much more compatible with a wide range of devices compared to the one on the RK3399 used on the ROCKPro64. This means a lot more devices should work (excluding dGPUs due to a lack of cache snooping ability).

==== Combo PHYs ====

[[File:rk3566 phy.png]]

Several of the I/O options on the RK3566 used in the Quartz64 are using the same I/O lines, meaning that they cannot be used at the same time. The above diagram illustrates how they are connected.

In particular, USB 3.0 and the SATA connector on the board are mutually exclusive, and the PCI-e 2.0 lane can be reconfigured into a second SATA port, though an adapter cable needs to be fashioned for this to be useful.

=== GPIO Pins (Quartz64 Model A) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX a
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX a
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT c
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

====Notes====
<ol style="list-style-type:lower-alpha">
<li>can be a PWM pin</li>
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
<li>low-pass filtered with cutoff of 220 MHz</li>
</ol>

Source: Page 28 of [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf the board schematics].

=== GPIO Pins (Quartz64 Model B) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| GPIO1_A0_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| GPIO1_A1_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_C4_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX
|-
| style="text-align:right;"| GPIO3_A1_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| GPIO3_A3_3V3
|-
| style="text-align:right;"| GPIO3_A2_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B0_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GPIO3_B1_3V3
|-
| style="text-align:right;"| 3.3V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| GPIO3_B2_3V3
|-
| style="text-align:right;"| GPIO4_C3_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO4_C5_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 21
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 22
| style="text-align:left;"| GPIO3_C1_3V3
|-
| style="text-align:right;"| GPIO4_C2_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 23
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 24
| style="text-align:left;"| GPIO4_C6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 25
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 26
| style="text-align:left;"| GPIO4_D1_3V3
|-
| style="text-align:right;"| I2C4_SDA_M0
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 27
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 28
| style="text-align:left;"| I2C4_SCL_M0
|-
| style="text-align:right;"| GPIO3_B3_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 29
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 30
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B4_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 31
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 32
| style="text-align:left;"| GPIO3_C2_3V3
|-
| style="text-align:right;"| GPIO3_C3_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 33
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 34
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_A4_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 35
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 36
| style="text-align:left;"| GPIO3_A7_3V3
|-
| style="text-align:right;"| GPIO1_A4_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 37
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 38
| style="text-align:left;"| GPIO3_A6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 39
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 40
| style="text-align:left;"| GPIO3_A5_3V3
|}

Source: Page 24 of [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf the board schematics].

== Quartz64 Board Information, Schematics, and Certifications ==

=== Model "A" ===
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Quartz64 Model "A" SBC Schematic ver 2.0 20210427 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V2.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Certifications:
** Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary. However, PINE64 still submit the SBC for FCC and CE certification and obtain the certificates to proof that SBC board is capable on passing the testing. Please note a final commercial product needs to performs its owns testing and obtains its owns certificates.
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20CE%20certification-S21051101701001.pdf Quartz64 model-A CE Certificate]
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20FCC%20certification-S21051101702001.pdf Quartz64 model-A FCC Certificate]

=== Model "B" ===

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID center-positive Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf Quartz64 Model "B" SBC Schematic ver 1.3 20220124 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_PCB_Components_Placement-V1.2_20211014.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]
* Please note that v1.2 and V1.3 schematic and component placement are identical, just some component value changed.

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK817%20datasheet%20V1.01.pdf Rockchip RK817 ver 1.01 datasheet for Quartz64 model A]
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for Quartz64 model B and SOQuartz]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
** [https://files.pine64.org/doc/datasheet/PineNote/TI%20PMU-TPS651851.pdf TPS65185x PMIC for E-Ink Enabled Electronic Paper Display Datasheet]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

=== Android 11 Production Test Build for Quartz64 model A SBC ===

==== Android 11 Stock Image [eMMC Boot] using DD method [20210604] ====
* DD image to eMMC module using USB adapter for eMMC module and boot. Highly recommend using [https://etcher.io/ Etcher]
* This is test build that used during product testing
* Please allow 3-5 minutes boot up time on first time for initialization
* DD image for 8GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-8GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): e4365753e584d9fce1b8f10f095eede6
*** File Size: 819MB
* DD image for 16GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-16GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 491c5f7744b0ca0b74ae76e607051836
*** File Size: 1.10GB
* DD image for 32GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-32GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 47a6f0cdac8bad06cb920743849a8894
*** File Size: 846MB
* DD image for 64GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-64GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 4e2fed6f5db0d55afdc8a142fc0c4fe1
*** File Size: 884MB

==== Android 11 Production Test Build for Quartz64 model A SBC [eMMC Boot] using ROCKChip tools method [20210604] ====
* Please unzip first and then using [https://files.pine64.org/os/Quartz64//android/RKDevTool_Release_v2.84.zip Rockchip Android tool ver 2.84] to flash in
* For Windows OS environment, please install the [https://files.pine64.org/os/Quartz64/android/DriverAssitant_v5.1.1.zip DriverAssistant v5.11] driver first
* This is test build that used during product testing
* The OTG port located at top USB 2.0 port on top of USB 3.0 port, needs USB type A to type A cable.
* Please allow 3-5 minutes boot up time on first time for initialization
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_20210604_stock_android11_emmcboot.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 800f867fdd0d1b2bd7822c156b6067e3
*** File Size: 812MB

=== Android 11 eink SDK for Quartz64 model A SBC ===
* The is the Android SDK build for 10.3" eink panel on Quartz64 model A SBC.
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_eink.android11_SDK.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 293a550584298de4fb95ceae18103672
** File Size: 72.88GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Enclosures ==

(Please expand this section with more cases known to work.)

=== Model "A" ===

All enclosures that fit the ROCKPro64 should fit the Quartz64 Model "A", as the I/O has been laid out the same on purpose.

* [["Model A" Acrylic Open Enclosure]] - but see the troubleshooting section below.
* [[ROCKPro64 ABS Enclosure]]
* [[Quartz64PremiumAluminiumCase|RockPro64 Premium Aluminium Case]]
* [[ROCKPro64#3D_printable_ITX_mounting_brackets]] (Not an enclosure but allows to mount the board in an ATX/ITX case)

=== Model "B" ===

* [["Model B" Acrylic Open Enclosure]]
* the ROCK64 aluminium enclosure '''does not''' work, as the DC input jack is placed differently

== Troubleshooting ==

=== Stability/Boot Issues With Missing Battery Shunt ===

If there is no battery plugged into the board, the jumper labelled "ON/OFF_BATT" must be in place. If this is set wrong, stability issues such as failures to boot will occur.

=== No Ethernet Connectivity ===

Make sure the kernel is built with <code>CONFIG_MOTORCOMM_PHY</code> set to <code>y</code>. Building it as a module (<code>m</code>) and then relying on module auto-loading is unlikely to work, because if the generic PHY driver is built in it will bind to the PHY first, unless you include the motorcomm module in your initramfs.

=== "Model A" Acrylic Case Doesn't Fit ===

The Quartz64 does not really fit onto the bottom plate of the [["Model A" Acrylic Open Enclosure]]. This is because the "Mic" connector at the bottom of the board interferes with one of the posts. A workaround is to find out which post that is (you have a 50% chance of guessing it right, accounting for rotating the board) and then filing away the corner of the post pointing inwards by a few millimetres.

[[File:Quartz64-audio-jack-spacer-issue.jpg]]

An alternate solution may be to place plastic spacers with a smaller outer diameter in between the acrylic bottom plate posts and the SBC board.

=== No GPU Acceleration with Debian "Bullseye" Userland ===

Debian Bullseye ships a Mesa version that is too old to contain the required patches for the RK356x SoC's GPU. You can (at your own risk) [https://wiki.debian.org/DebianTesting use the current Debian Testing version ], called "Bookworm".

[[Category:Quartz64]]

Quartz64

2022-06-07T08:09:53Z

Bullet64: /* GPIO Pins (Quartz64 Model B) */

[[File:Quartz64modelb.png|400px|thumb|right|The Quartz64 Model B]]

The '''Quartz64''' is the most recent Single Board Computer offering from PINE64, with Model A initially released in June of 2021 and Model B in May of 2022. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software releases ==

{{warning|Software for the Quartz64 is still early in development, and therefore currently lacks features such as the ability to produce video output. You are strongly encouraged to procure a 3.3V UART serial adapter capable of running at 1.5 mbauds, such as [https://pine64.com/product/serial-console-woodpecker-edition/ the woodpecker] if you want to use a Quartz64 at this stage.}}

=== Manjaro ARM ===
[[File:Manjaro.png|right|100px]]

Manjaro ARM is a user friendly rolling release distribution, based on Arch Linux ARM.

==== Manjaro ARM with no desktop ====

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
Note, manjaro currently ships with the linux-rc kernel. Currently (and temporarily/as of writing), usb3, pcie and sata devices will not be found unless you swap to the linux-quartz64 kernel <code>pacman -S linux-quartz64</code>.
* [https://github.com/manjaro-arm/quartz64-a-images/releases Images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

==== Manjaro ARM with desktop environment ====

Since '''Dev 20211117''' with hdmi output (linux-rc)

* Gnome
* KDE Plasma
* Mate
* Sway
* XFCE

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

=== pgwipeout's Quartz64 CI ===

pgwipeout provides continuously rebuilt set of images for Quartz64 devices which includes a Debian installer and a buildroot rescue environment. It is aimed at advanced users who generally know their way around a Linux system, and as a baseline for whether something is working or not. Works on both SD cards and eMMC, uses pgwipeout's patched kernel. Kernels aren't auto-updated on the installed system, so the user manually has to do this by mounting the actual correct boot partition.

'''Download:''' https://gitlab.com/pgwipeout/quartz64_ci/-/pipelines (Click the three dots on the right, download the merge-job archive.)

For Quartz64 Model A, flash <tt>rk3566-quartz64-a.dtb.img.xz</tt>. On Linux, you can for example do this as follows, assuming your target device is <tt>/dev/sdX</tt>:

sudo -i; xzcat /path/to/rk3566-quartz64-a.dtb.img.xz > /dev/sdX

For Quartz64 Model B, use <tt>rk3566-quartz64-b.dtb.img.xz</tt> instead.

For line by line instructions to boot Quartz64 CI on a microSD card and use it to install Debian onto an eMMC follow these instructions https://wiki.pine64.org/wiki/Installing_Debian_on_the_Quartz64

=== Arch Linux ARM (Unofficial) ===

See [[Installing Arch Linux ARM On The Quartz64]] for detailed instructions.

=== Tianocore EDK II port by jmcneill ===

This (as of 2021-12-30) is a work in progress to enable UEFI enabled systems, and is able to bring up SD, eMMC, USB, PCIe with SATA and NVMe, HDMI, thermal sensors, TRNG, as well as general Cortex A-55 features. Known to work with NetBSD -current, and the ESXi Arm fling version 1.8.

* [https://github.com/jaredmcneill/quartz64_uefi jmcneill's Quartz64 UEFI Github]

The sdcard image should be written to an microSD card and installed. Currently, using this card also for the OS may be problematic.

=== NetBSD ===

NetBSD relies upon the UEFI support in Tianocore. Before NetBSD 10 is released, the latest version of NetBSD-current should be used:

* [http://nycdn.netbsd.org/pub/NetBSD-daily/HEAD/ NetBSD daily builds top level] from inside here, navigate to a date, and inside the images/ subdirectory are installable images. Use the one called "NetBSD-<version>-evbarm-aarch64-install.img.gz". This image can be written to a supported device, such as the eMMC interface, any USB storage device, NVMe, and PCIe AHCI SATA are all supported with builds after 2022-01-15.

* Currently this can not be shared with the EDK2 port, ie, microSD for EDK2 and some other media for NetBSD.

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support
* [https://www.cnx-software.com/2020/12/01/rockchip-rk3568-processor-to-power-edge-computing-and-nvr-applications 22nm process, believed to be FD-SOI]

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB (SOQuartz only), 4GB, 8GB LPDDR4.

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB
** Model A: 2 USB 2.0 host ports, 1 USB 2.0 OTG port, 1 USB 3.0 host port
** Model B: 1 USB 2.0 host port, 1 USB 2.0 OTG port, 1 USB 3.0 host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 16GB up to 128GB

==== eMMC Speeds ====

On a 64 GB eMMC module:

$ sudo hdparm -tT /dev/mmcblk1

/dev/mmcblk1:
Timing cached reads: 2368 MB in 2.00 seconds = 1184.46 MB/sec
Timing buffered disk reads: 452 MB in 3.01 seconds = 149.98 MB/sec

=== Expansion Ports ===
* HDMI
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints
** On Model A, the slot provides 10W of power for the 3.3V supply and however much power your 12V input power supply provides on the 12V supply

The PCIe implementation on the RK3566 is much more compatible with a wide range of devices compared to the one on the RK3399 used on the ROCKPro64. This means a lot more devices should work (excluding dGPUs due to a lack of cache snooping ability).

==== Combo PHYs ====

[[File:rk3566 phy.png]]

Several of the I/O options on the RK3566 used in the Quartz64 are using the same I/O lines, meaning that they cannot be used at the same time. The above diagram illustrates how they are connected.

In particular, USB 3.0 and the SATA connector on the board are mutually exclusive, and the PCI-e 2.0 lane can be reconfigured into a second SATA port, though an adapter cable needs to be fashioned for this to be useful.

=== GPIO Pins (Quartz64 Model A) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX a
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX a
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT c
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

====Notes====
<ol style="list-style-type:lower-alpha">
<li>can be a PWM pin</li>
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
<li>low-pass filtered with cutoff of 220 MHz</li>
</ol>

Source: Page 28 of [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf the board schematics].

=== GPIO Pins (Quartz64 Model B) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| GPIO1_A0_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| GPIO1_A1_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_C4_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX
|-
| style="text-align:right;"| GPIO3_A1_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| GPIO3_A3_3V3
|-
| style="text-align:right;"| GPIO3_A2_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B0_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GPIO3_B1_3V3
|-
| style="text-align:right;"| 3.3V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| GPIO3_B2_3V3
|-
| style="text-align:right;"| GPIO4_C3_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO4_C5_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 21
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 22
| style="text-align:left;"| GPIO3_C1_3V3
|-
| style="text-align:right;"| GPIO4_C2_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 23
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 24
| style="text-align:left;"| GPIO4_C6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 25
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 26
| style="text-align:left;"| GPIO4_D1_3V3
|-
| style="text-align:right;"| I2C4_SDA_M0
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 27
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 28
| style="text-align:left;"| I2C4_SCL_M0
|-
| style="text-align:right;"| GPIO3_B3_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 29
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 30
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B4_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 31
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 32
| style="text-align:left;"| GPIO3_C2_3V3
|-
| style="text-align:right;"| GPIO3_C3_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 33
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 34
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_A4_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 35
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 36
| style="text-align:left;"| GPIO3_A7_3V3
|-
| style="text-align:right;"| GPIO1_A4_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 37
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 38
| style="text-align:left;"| GPIO3_A6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 39
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 40
| style="text-align:left;"| GPIO3_A5_3V3
|}

Source: Page 24 of [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf].

== Quartz64 Board Information, Schematics, and Certifications ==

=== Model "A" ===
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Quartz64 Model "A" SBC Schematic ver 2.0 20210427 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V2.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Certifications:
** Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary. However, PINE64 still submit the SBC for FCC and CE certification and obtain the certificates to proof that SBC board is capable on passing the testing. Please note a final commercial product needs to performs its owns testing and obtains its owns certificates.
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20CE%20certification-S21051101701001.pdf Quartz64 model-A CE Certificate]
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20FCC%20certification-S21051101702001.pdf Quartz64 model-A FCC Certificate]

=== Model "B" ===

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID center-positive Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf Quartz64 Model "B" SBC Schematic ver 1.3 20220124 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_PCB_Components_Placement-V1.2_20211014.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]
* Please note that v1.2 and V1.3 schematic and component placement are identical, just some component value changed.

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK817%20datasheet%20V1.01.pdf Rockchip RK817 ver 1.01 datasheet for Quartz64 model A]
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for Quartz64 model B and SOQuartz]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
** [https://files.pine64.org/doc/datasheet/PineNote/TI%20PMU-TPS651851.pdf TPS65185x PMIC for E-Ink Enabled Electronic Paper Display Datasheet]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

=== Android 11 Production Test Build for Quartz64 model A SBC ===

==== Android 11 Stock Image [eMMC Boot] using DD method [20210604] ====
* DD image to eMMC module using USB adapter for eMMC module and boot. Highly recommend using [https://etcher.io/ Etcher]
* This is test build that used during product testing
* Please allow 3-5 minutes boot up time on first time for initialization
* DD image for 8GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-8GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): e4365753e584d9fce1b8f10f095eede6
*** File Size: 819MB
* DD image for 16GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-16GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 491c5f7744b0ca0b74ae76e607051836
*** File Size: 1.10GB
* DD image for 32GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-32GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 47a6f0cdac8bad06cb920743849a8894
*** File Size: 846MB
* DD image for 64GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-64GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 4e2fed6f5db0d55afdc8a142fc0c4fe1
*** File Size: 884MB

==== Android 11 Production Test Build for Quartz64 model A SBC [eMMC Boot] using ROCKChip tools method [20210604] ====
* Please unzip first and then using [https://files.pine64.org/os/Quartz64//android/RKDevTool_Release_v2.84.zip Rockchip Android tool ver 2.84] to flash in
* For Windows OS environment, please install the [https://files.pine64.org/os/Quartz64/android/DriverAssitant_v5.1.1.zip DriverAssistant v5.11] driver first
* This is test build that used during product testing
* The OTG port located at top USB 2.0 port on top of USB 3.0 port, needs USB type A to type A cable.
* Please allow 3-5 minutes boot up time on first time for initialization
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_20210604_stock_android11_emmcboot.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 800f867fdd0d1b2bd7822c156b6067e3
*** File Size: 812MB

=== Android 11 eink SDK for Quartz64 model A SBC ===
* The is the Android SDK build for 10.3" eink panel on Quartz64 model A SBC.
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_eink.android11_SDK.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 293a550584298de4fb95ceae18103672
** File Size: 72.88GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Enclosures ==

(Please expand this section with more cases known to work.)

=== Model "A" ===

All enclosures that fit the ROCKPro64 should fit the Quartz64 Model "A", as the I/O has been laid out the same on purpose.

* [["Model A" Acrylic Open Enclosure]] - but see the troubleshooting section below.
* [[ROCKPro64 ABS Enclosure]]
* [[Quartz64PremiumAluminiumCase|RockPro64 Premium Aluminium Case]]
* [[ROCKPro64#3D_printable_ITX_mounting_brackets]] (Not an enclosure but allows to mount the board in an ATX/ITX case)

=== Model "B" ===

* [["Model B" Acrylic Open Enclosure]]
* the ROCK64 aluminium enclosure '''does not''' work, as the DC input jack is placed differently

== Troubleshooting ==

=== Stability/Boot Issues With Missing Battery Shunt ===

If there is no battery plugged into the board, the jumper labelled "ON/OFF_BATT" must be in place. If this is set wrong, stability issues such as failures to boot will occur.

=== No Ethernet Connectivity ===

Make sure the kernel is built with <code>CONFIG_MOTORCOMM_PHY</code> set to <code>y</code>. Building it as a module (<code>m</code>) and then relying on module auto-loading is unlikely to work, because if the generic PHY driver is built in it will bind to the PHY first, unless you include the motorcomm module in your initramfs.

=== "Model A" Acrylic Case Doesn't Fit ===

The Quartz64 does not really fit onto the bottom plate of the [["Model A" Acrylic Open Enclosure]]. This is because the "Mic" connector at the bottom of the board interferes with one of the posts. A workaround is to find out which post that is (you have a 50% chance of guessing it right, accounting for rotating the board) and then filing away the corner of the post pointing inwards by a few millimetres.

[[File:Quartz64-audio-jack-spacer-issue.jpg]]

An alternate solution may be to place plastic spacers with a smaller outer diameter in between the acrylic bottom plate posts and the SBC board.

=== No GPU Acceleration with Debian "Bullseye" Userland ===

Debian Bullseye ships a Mesa version that is too old to contain the required patches for the RK356x SoC's GPU. You can (at your own risk) [https://wiki.debian.org/DebianTesting use the current Debian Testing version ], called "Bookworm".

[[Category:Quartz64]]

Quartz64

2022-06-07T08:08:24Z

Bullet64: /* GPIO Pins (Quartz64 Model A) */

[[File:Quartz64modelb.png|400px|thumb|right|The Quartz64 Model B]]

The '''Quartz64''' is the most recent Single Board Computer offering from PINE64, with Model A initially released in June of 2021 and Model B in May of 2022. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software releases ==

{{warning|Software for the Quartz64 is still early in development, and therefore currently lacks features such as the ability to produce video output. You are strongly encouraged to procure a 3.3V UART serial adapter capable of running at 1.5 mbauds, such as [https://pine64.com/product/serial-console-woodpecker-edition/ the woodpecker] if you want to use a Quartz64 at this stage.}}

=== Manjaro ARM ===
[[File:Manjaro.png|right|100px]]

Manjaro ARM is a user friendly rolling release distribution, based on Arch Linux ARM.

==== Manjaro ARM with no desktop ====

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
Note, manjaro currently ships with the linux-rc kernel. Currently (and temporarily/as of writing), usb3, pcie and sata devices will not be found unless you swap to the linux-quartz64 kernel <code>pacman -S linux-quartz64</code>.
* [https://github.com/manjaro-arm/quartz64-a-images/releases Images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

==== Manjaro ARM with desktop environment ====

Since '''Dev 20211117''' with hdmi output (linux-rc)

* Gnome
* KDE Plasma
* Mate
* Sway
* XFCE

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

=== pgwipeout's Quartz64 CI ===

pgwipeout provides continuously rebuilt set of images for Quartz64 devices which includes a Debian installer and a buildroot rescue environment. It is aimed at advanced users who generally know their way around a Linux system, and as a baseline for whether something is working or not. Works on both SD cards and eMMC, uses pgwipeout's patched kernel. Kernels aren't auto-updated on the installed system, so the user manually has to do this by mounting the actual correct boot partition.

'''Download:''' https://gitlab.com/pgwipeout/quartz64_ci/-/pipelines (Click the three dots on the right, download the merge-job archive.)

For Quartz64 Model A, flash <tt>rk3566-quartz64-a.dtb.img.xz</tt>. On Linux, you can for example do this as follows, assuming your target device is <tt>/dev/sdX</tt>:

sudo -i; xzcat /path/to/rk3566-quartz64-a.dtb.img.xz > /dev/sdX

For Quartz64 Model B, use <tt>rk3566-quartz64-b.dtb.img.xz</tt> instead.

For line by line instructions to boot Quartz64 CI on a microSD card and use it to install Debian onto an eMMC follow these instructions https://wiki.pine64.org/wiki/Installing_Debian_on_the_Quartz64

=== Arch Linux ARM (Unofficial) ===

See [[Installing Arch Linux ARM On The Quartz64]] for detailed instructions.

=== Tianocore EDK II port by jmcneill ===

This (as of 2021-12-30) is a work in progress to enable UEFI enabled systems, and is able to bring up SD, eMMC, USB, PCIe with SATA and NVMe, HDMI, thermal sensors, TRNG, as well as general Cortex A-55 features. Known to work with NetBSD -current, and the ESXi Arm fling version 1.8.

* [https://github.com/jaredmcneill/quartz64_uefi jmcneill's Quartz64 UEFI Github]

The sdcard image should be written to an microSD card and installed. Currently, using this card also for the OS may be problematic.

=== NetBSD ===

NetBSD relies upon the UEFI support in Tianocore. Before NetBSD 10 is released, the latest version of NetBSD-current should be used:

* [http://nycdn.netbsd.org/pub/NetBSD-daily/HEAD/ NetBSD daily builds top level] from inside here, navigate to a date, and inside the images/ subdirectory are installable images. Use the one called "NetBSD-<version>-evbarm-aarch64-install.img.gz". This image can be written to a supported device, such as the eMMC interface, any USB storage device, NVMe, and PCIe AHCI SATA are all supported with builds after 2022-01-15.

* Currently this can not be shared with the EDK2 port, ie, microSD for EDK2 and some other media for NetBSD.

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support
* [https://www.cnx-software.com/2020/12/01/rockchip-rk3568-processor-to-power-edge-computing-and-nvr-applications 22nm process, believed to be FD-SOI]

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB (SOQuartz only), 4GB, 8GB LPDDR4.

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB
** Model A: 2 USB 2.0 host ports, 1 USB 2.0 OTG port, 1 USB 3.0 host port
** Model B: 1 USB 2.0 host port, 1 USB 2.0 OTG port, 1 USB 3.0 host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 16GB up to 128GB

==== eMMC Speeds ====

On a 64 GB eMMC module:

$ sudo hdparm -tT /dev/mmcblk1

/dev/mmcblk1:
Timing cached reads: 2368 MB in 2.00 seconds = 1184.46 MB/sec
Timing buffered disk reads: 452 MB in 3.01 seconds = 149.98 MB/sec

=== Expansion Ports ===
* HDMI
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints
** On Model A, the slot provides 10W of power for the 3.3V supply and however much power your 12V input power supply provides on the 12V supply

The PCIe implementation on the RK3566 is much more compatible with a wide range of devices compared to the one on the RK3399 used on the ROCKPro64. This means a lot more devices should work (excluding dGPUs due to a lack of cache snooping ability).

==== Combo PHYs ====

[[File:rk3566 phy.png]]

Several of the I/O options on the RK3566 used in the Quartz64 are using the same I/O lines, meaning that they cannot be used at the same time. The above diagram illustrates how they are connected.

In particular, USB 3.0 and the SATA connector on the board are mutually exclusive, and the PCI-e 2.0 lane can be reconfigured into a second SATA port, though an adapter cable needs to be fashioned for this to be useful.

=== GPIO Pins (Quartz64 Model A) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX a
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX a
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT c
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

====Notes====
<ol style="list-style-type:lower-alpha">
<li>can be a PWM pin</li>
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
<li>low-pass filtered with cutoff of 220 MHz</li>
</ol>

Source: Page 28 of [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf the board schematics].

=== GPIO Pins (Quartz64 Model B) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| GPIO1_A0_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| GPIO1_A1_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_C4_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX
|-
| style="text-align:right;"| GPIO3_A1_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| GPIO3_A3_3V3
|-
| style="text-align:right;"| GPIO3_A2_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B0_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GPIO3_B1_3V3
|-
| style="text-align:right;"| 3.3V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| GPIO3_B2_3V3
|-
| style="text-align:right;"| GPIO4_C3_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO4_C5_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 21
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 22
| style="text-align:left;"| GPIO3_C1_3V3
|-
| style="text-align:right;"| GPIO4_C2_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 23
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 24
| style="text-align:left;"| GPIO4_C6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 25
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 26
| style="text-align:left;"| GPIO4_D1_3V3
|-
| style="text-align:right;"| I2C4_SDA_M0
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 27
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 28
| style="text-align:left;"| I2C4_SCL_M0
|-
| style="text-align:right;"| GPIO3_B3_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 29
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 30
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_B4_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 31
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 32
| style="text-align:left;"| GPIO3_C2_3V3
|-
| style="text-align:right;"| GPIO3_C3_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 33
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 34
| style="text-align:left;"| GND
|-
| style="text-align:right;"| GPIO3_A4_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 35
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 36
| style="text-align:left;"| GPIO3_A7_3V3
|-
| style="text-align:right;"| GPIO1_A4_3V3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 37
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 38
| style="text-align:left;"| GPIO3_A6_3V3
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 39
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 40
| style="text-align:left;"| GPIO3_A5_3V3
|}

== Quartz64 Board Information, Schematics, and Certifications ==

=== Model "A" ===
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Quartz64 Model "A" SBC Schematic ver 2.0 20210427 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V2.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Certifications:
** Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary. However, PINE64 still submit the SBC for FCC and CE certification and obtain the certificates to proof that SBC board is capable on passing the testing. Please note a final commercial product needs to performs its owns testing and obtains its owns certificates.
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20CE%20certification-S21051101701001.pdf Quartz64 model-A CE Certificate]
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20FCC%20certification-S21051101702001.pdf Quartz64 model-A FCC Certificate]

=== Model "B" ===

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID center-positive Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf Quartz64 Model "B" SBC Schematic ver 1.3 20220124 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_PCB_Components_Placement-V1.2_20211014.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]
* Please note that v1.2 and V1.3 schematic and component placement are identical, just some component value changed.

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK817%20datasheet%20V1.01.pdf Rockchip RK817 ver 1.01 datasheet for Quartz64 model A]
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for Quartz64 model B and SOQuartz]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
** [https://files.pine64.org/doc/datasheet/PineNote/TI%20PMU-TPS651851.pdf TPS65185x PMIC for E-Ink Enabled Electronic Paper Display Datasheet]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

=== Android 11 Production Test Build for Quartz64 model A SBC ===

==== Android 11 Stock Image [eMMC Boot] using DD method [20210604] ====
* DD image to eMMC module using USB adapter for eMMC module and boot. Highly recommend using [https://etcher.io/ Etcher]
* This is test build that used during product testing
* Please allow 3-5 minutes boot up time on first time for initialization
* DD image for 8GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-8GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): e4365753e584d9fce1b8f10f095eede6
*** File Size: 819MB
* DD image for 16GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-16GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 491c5f7744b0ca0b74ae76e607051836
*** File Size: 1.10GB
* DD image for 32GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-32GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 47a6f0cdac8bad06cb920743849a8894
*** File Size: 846MB
* DD image for 64GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-64GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 4e2fed6f5db0d55afdc8a142fc0c4fe1
*** File Size: 884MB

==== Android 11 Production Test Build for Quartz64 model A SBC [eMMC Boot] using ROCKChip tools method [20210604] ====
* Please unzip first and then using [https://files.pine64.org/os/Quartz64//android/RKDevTool_Release_v2.84.zip Rockchip Android tool ver 2.84] to flash in
* For Windows OS environment, please install the [https://files.pine64.org/os/Quartz64/android/DriverAssitant_v5.1.1.zip DriverAssistant v5.11] driver first
* This is test build that used during product testing
* The OTG port located at top USB 2.0 port on top of USB 3.0 port, needs USB type A to type A cable.
* Please allow 3-5 minutes boot up time on first time for initialization
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_20210604_stock_android11_emmcboot.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 800f867fdd0d1b2bd7822c156b6067e3
*** File Size: 812MB

=== Android 11 eink SDK for Quartz64 model A SBC ===
* The is the Android SDK build for 10.3" eink panel on Quartz64 model A SBC.
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_eink.android11_SDK.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 293a550584298de4fb95ceae18103672
** File Size: 72.88GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Enclosures ==

(Please expand this section with more cases known to work.)

=== Model "A" ===

All enclosures that fit the ROCKPro64 should fit the Quartz64 Model "A", as the I/O has been laid out the same on purpose.

* [["Model A" Acrylic Open Enclosure]] - but see the troubleshooting section below.
* [[ROCKPro64 ABS Enclosure]]
* [[Quartz64PremiumAluminiumCase|RockPro64 Premium Aluminium Case]]
* [[ROCKPro64#3D_printable_ITX_mounting_brackets]] (Not an enclosure but allows to mount the board in an ATX/ITX case)

=== Model "B" ===

* [["Model B" Acrylic Open Enclosure]]
* the ROCK64 aluminium enclosure '''does not''' work, as the DC input jack is placed differently

== Troubleshooting ==

=== Stability/Boot Issues With Missing Battery Shunt ===

If there is no battery plugged into the board, the jumper labelled "ON/OFF_BATT" must be in place. If this is set wrong, stability issues such as failures to boot will occur.

=== No Ethernet Connectivity ===

Make sure the kernel is built with <code>CONFIG_MOTORCOMM_PHY</code> set to <code>y</code>. Building it as a module (<code>m</code>) and then relying on module auto-loading is unlikely to work, because if the generic PHY driver is built in it will bind to the PHY first, unless you include the motorcomm module in your initramfs.

=== "Model A" Acrylic Case Doesn't Fit ===

The Quartz64 does not really fit onto the bottom plate of the [["Model A" Acrylic Open Enclosure]]. This is because the "Mic" connector at the bottom of the board interferes with one of the posts. A workaround is to find out which post that is (you have a 50% chance of guessing it right, accounting for rotating the board) and then filing away the corner of the post pointing inwards by a few millimetres.

[[File:Quartz64-audio-jack-spacer-issue.jpg]]

An alternate solution may be to place plastic spacers with a smaller outer diameter in between the acrylic bottom plate posts and the SBC board.

=== No GPU Acceleration with Debian "Bullseye" Userland ===

Debian Bullseye ships a Mesa version that is too old to contain the required patches for the RK356x SoC's GPU. You can (at your own risk) [https://wiki.debian.org/DebianTesting use the current Debian Testing version ], called "Bookworm".

[[Category:Quartz64]]

Quartz64

2022-05-21T06:00:51Z

Bullet64: /* Manjaro ARM with no desktop */

[[File:Quartz64modelb.png|400px|thumb|right|The Quartz64 Model B]]

The '''Quartz64''' is the most recent Single Board Computer offering from PINE64, with Model A initially released in June of 2021 and Model B in May of 2022. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software releases ==

{{warning|Software for the Quartz64 is still early in development, and therefore currently lacks features such as the ability to produce video output. You are strongly encouraged to procure a 3.3V UART serial adapter capable of running at 1.5 mbauds, such as [https://pine64.com/product/serial-console-woodpecker-edition/ the woodpecker] if you want to use a Quartz64 at this stage.}}

=== Manjaro ARM ===
[[File:Manjaro.png|right|100px]]

Manjaro ARM is a user friendly rolling release distribution, based on Arch Linux ARM.

==== Manjaro ARM with no desktop ====

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
Note, manjaro currently ships with the linux-rc kernel. Currently (and temporarily/as of writing), usb3, pcie and sata devices will not be found unless you swap to the linux-quartz64 kernel <code>pacman -S linux-quartz64</code>.
* [https://github.com/manjaro-arm/quartz64-a-images/releases Images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

==== Manjaro ARM with desktop environment ====

Since '''Dev 20211117''' with hdmi output (linux-rc)

* Gnome
* KDE Plasma
* Mate
* Sway
* XFCE

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images for Model A on GitHub]
* [https://github.com/manjaro-arm/quartz64-b-images/releases Images for Model B on GitHub]

=== pgwipeout's Quartz64 CI ===

pgwipeout provides continuously rebuilt set of images for Quartz64 devices which includes a Debian installer and a buildroot rescue environment. It is aimed at advanced users who generally know their way around a Linux system, and as a baseline for whether something is working or not. Works on both SD cards and eMMC, uses pgwipeout's patched kernel. Kernels aren't auto-updated on the installed system, so the user manually has to do this by mounting the actual correct boot partition.

'''Download:''' https://gitlab.com/pgwipeout/quartz64_ci/-/pipelines (Click the three dots on the right, download the merge-job archive.)

For Quartz64 Model A, flash <tt>rk3566-quartz64-a.dtb.img.xz</tt>. On Linux, you can for example do this as follows, assuming your target device is <tt>/dev/sdX</tt>:

sudo -i; xzcat /path/to/rk3566-quartz64-a.dtb.img.xz > /dev/sdX

For Quartz64 Model B, use <tt>rk3566-quartz64-b.dtb.img.xz</tt> instead.

For line by line instructions to boot Quartz64 CI on a microSD card and use it to install Debian onto an eMMC follow these instructions https://wiki.pine64.org/wiki/Installing_Debian_on_the_Quartz64

=== Arch Linux ARM (Unofficial, Highly Experimental) ===

See [[Installing Arch Linux ARM On The Quartz64]] for detailed instructions. Users who are not feeling adventurous are advised to hold off until the official Arch Linux ARM kernel has its build config adjusted.

=== Tianocore EDK II port by jmcneill ===

This (as of 2021-12-30) is a work in progress to enable UEFI enabled systems, and is able to bring up SD, eMMC, USB, PCIe with SATA and NVMe, HDMI, thermal sensors, TRNG, as well as general Cortex A-55 features. Known to work with NetBSD -current, and the ESXi Arm fling version 1.8.

* [https://github.com/jaredmcneill/quartz64_uefi jmcneill's Quartz64 UEFI Github]

The sdcard image should be written to an microSD card and installed. Currently, using this card also for the OS may be problematic.

=== NetBSD ===

NetBSD relies upon the UEFI support in Tianocore. Before NetBSD 10 is released, the latest version of NetBSD-current should be used:

* [http://nycdn.netbsd.org/pub/NetBSD-daily/HEAD/ NetBSD daily builds top level] from inside here, navigate to a date, and inside the images/ subdirectory are installable images. Use the one called "NetBSD-<version>-evbarm-aarch64-install.img.gz". This image can be written to a supported device, such as the eMMC interface, any USB storage device, NVMe, and PCIe AHCI SATA are all supported with builds after 2022-01-15.

* Currently this can not be shared with the EDK2 port, ie, microSD for EDK2 and some other media for NetBSD.

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support
* [https://www.cnx-software.com/2020/12/01/rockchip-rk3568-processor-to-power-edge-computing-and-nvr-applications 22nm process, believed to be FD-SOI]

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB (SOQuartz only), 4GB, 8GB LPDDR4.

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB
** Model A: 2 USB 2.0 host ports, 1 USB 2.0 OTG port, 1 USB 3.0 host port
** Model B: 1 USB 2.0 host port, 1 USB 2.0 OTG port, 1 USB 3.0 host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 16GB up to 128GB

==== eMMC Speeds ====

On a 64 GB eMMC module:

$ sudo hdparm -tT /dev/mmcblk1

/dev/mmcblk1:
Timing cached reads: 2368 MB in 2.00 seconds = 1184.46 MB/sec
Timing buffered disk reads: 452 MB in 3.01 seconds = 149.98 MB/sec

=== Expansion Ports ===
* HDMI
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints
** On Model A, the slot provides 10W of power for the 3.3V supply and however much power your 12V input power supply provides on the 12V supply

The PCIe implementation on the RK3566 is much more compatible with a wide range of devices compared to the one on the RK3399 used on the ROCKPro64. This means a lot more devices should work (excluding dGPUs due to a lack of cache snooping ability).

==== Combo PHYs ====

[[File:rk3566 phy.png]]

Several of the I/O options on the RK3566 used in the Quartz64 are using the same I/O lines, meaning that they cannot be used at the same time. The above diagram illustrates how they are connected.

In particular, USB 3.0 and the SATA connector on the board are mutually exclusive, and the PCI-e 2.0 lane can be reconfigured into a second SATA port, though an adapter cable needs to be fashioned for this to be useful.

=== GPIO Pins (Quartz64 Model A) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX a
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX a
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT c
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

====Notes====
<ol style="list-style-type:lower-alpha">
<li>can be a PWM pin</li>
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
<li>low-pass filtered with cutoff of 220 MHz</li>
</ol>

Source: Page 28 of [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf the board schematics].

== Quartz64 Board Information, Schematics, and Certifications ==

=== Model "A" ===
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Quartz64 Model "A" SBC Schematic ver 2.0 20210427 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V2.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Certifications:
** Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary. However, PINE64 still submit the SBC for FCC and CE certification and obtain the certificates to proof that SBC board is capable on passing the testing. Please note a final commercial product needs to performs its owns testing and obtains its owns certificates.
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20CE%20certification-S21051101701001.pdf Quartz64 model-A CE Certificate]
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20FCC%20certification-S21051101702001.pdf Quartz64 model-A FCC Certificate]

=== Model "B" ===

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID center-positive Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_Schematic-V1.3_20220124.pdf Quartz64 Model "B" SBC Schematic ver 1.3 20220124 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-B_PCB_Components_Placement-V1.2_20211014.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]
* Please note that v1.2 and V1.3 schematic and component placement are identical, just some component value changed.

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK817%20datasheet%20V1.01.pdf Rockchip RK817 ver 1.01 datasheet for Quartz64 model A]
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for Quartz64 model B and SOQuartz]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
** [https://files.pine64.org/doc/datasheet/PineNote/TI%20PMU-TPS651851.pdf TPS65185x PMIC for E-Ink Enabled Electronic Paper Display Datasheet]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

=== Android 11 Production Test Build for Quartz64 model A SBC ===

==== Android 11 Stock Image [eMMC Boot] using DD method [20210604] ====
* DD image to eMMC module using USB adapter for eMMC module and boot. Highly recommend using [https://etcher.io/ Etcher]
* This is test build that used during product testing
* Please allow 3-5 minutes boot up time on first time for initialization
* DD image for 8GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-8GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): e4365753e584d9fce1b8f10f095eede6
*** File Size: 819MB
* DD image for 16GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-16GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 491c5f7744b0ca0b74ae76e607051836
*** File Size: 1.10GB
* DD image for 32GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-32GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 47a6f0cdac8bad06cb920743849a8894
*** File Size: 846MB
* DD image for 64GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-64GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 4e2fed6f5db0d55afdc8a142fc0c4fe1
*** File Size: 884MB

==== Android 11 Production Test Build for Quartz64 model A SBC [eMMC Boot] using ROCKChip tools method [20210604] ====
* Please unzip first and then using [https://files.pine64.org/os/Quartz64//android/RKDevTool_Release_v2.84.zip Rockchip Android tool ver 2.84] to flash in
* For Windows OS environment, please install the [https://files.pine64.org/os/Quartz64/android/DriverAssitant_v5.1.1.zip DriverAssistant v5.11] driver first
* This is test build that used during product testing
* The OTG port located at top USB 2.0 port on top of USB 3.0 port, needs USB type A to type A cable.
* Please allow 3-5 minutes boot up time on first time for initialization
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_20210604_stock_android11_emmcboot.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 800f867fdd0d1b2bd7822c156b6067e3
*** File Size: 812MB

=== Android 11 eink SDK for Quartz64 model A SBC ===
* The is the Android SDK build for 10.3" eink panel on Quartz64 model A SBC.
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_eink.android11_SDK.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 293a550584298de4fb95ceae18103672
** File Size: 72.88GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Enclosures ==

(Please expand this section with more cases known to work.)

=== Model "A" ===

All enclosures that fit the ROCKPro64 should fit the Quartz64 Model "A", as the I/O has been laid out the same on purpose.

* [["Model A" Acrylic Open Enclosure]] - but see the troubleshooting section below.
* [[ROCKPro64 ABS Enclosure]]
* [[Quartz64PremiumAluminiumCase|RockPro64 Premium Aluminium Case]]
* [[ROCKPro64#3D_printable_ITX_mounting_brackets]] (Not an enclosure but allows to mount the board in an ATX/ITX case)

=== Model "B" ===

* [["Model B" Acrylic Open Enclosure]]
* the ROCK64 aluminium enclosure '''does not''' work, as the DC input jack is placed differently

== Troubleshooting ==

=== Stability/Boot Issues With Missing Battery Shunt ===

If there is no battery plugged into the board, the jumper labelled "ON/OFF_BATT" must be in place. If this is set wrong, stability issues such as failures to boot will occur.

=== No Ethernet Connectivity ===

Make sure the kernel is built with <code>CONFIG_MOTORCOMM_PHY</code> set to <code>y</code>. Building it as a module (<code>m</code>) and then relying on module auto-loading is unlikely to work, because if the generic PHY driver is built in it will bind to the PHY first, unless you include the motorcomm module in your initramfs.

=== "Model A" Acrylic Case Doesn't Fit ===

The Quartz64 does not really fit onto the bottom plate of the [["Model A" Acrylic Open Enclosure]]. This is because the "Mic" connector at the bottom of the board interferes with one of the posts. A workaround is to find out which post that is (you have a 50% chance of guessing it right, accounting for rotating the board) and then filing away the corner of the post pointing inwards by a few millimetres.

[[File:Quartz64-audio-jack-spacer-issue.jpg]]

An alternate solution may be to place plastic spacers with a smaller outer diameter in between the acrylic bottom plate posts and the SBC board.

=== No GPU Acceleration with Debian "Bullseye" Userland ===

Debian Bullseye ships a Mesa version that is too old to contain the required patches for the RK356x SoC's GPU. You can (at your own risk) [https://wiki.debian.org/DebianTesting use the current Debian Testing version ], called "Bookworm".

[[Category:Quartz64]]

Quartz64

2021-11-23T21:09:25Z

Bullet64: /* Manjaro ARM with desktop */

[[File:Quartz64modelb.png|400px|thumb|right|The Quartz64 Model B]]

The '''Quartz64''' is the most recent Single Board Computer offering from PINE64, initially released in June of 2021. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software releases ==

{{warning|Software for the Quartz64 is still early in development, and therefore currently lacks features such as the ability to produce video output. You are strongly encouraged to procure a 3.3V UART serial adapter capable of running at 1.5 mbauds, such as [https://pine64.com/product/serial-console-woodpecker-edition/ the woodpecker] if you want to use a Quartz64 at this stage.}}

=== Manjaro ARM ===
[[File:Manjaro.png|right|100px]]

Manjaro ARM is a user friendly rolling release distribution, based on Arch Linux ARM.

==== Manjaro ARM with no desktop ====

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images on Github]

==== Manjaro ARM with desktop environment ====

Since '''Dev 20211117''' with hdmi output (linux-rc)

* Gnome
* KDE Plasma
* Mate
* Sway
* XFCE

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images on Github]

Note: Video out only working on 4 GB boards with 1080p monitors right now as the VOP2 patches are very early.

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support
* [https://www.cnx-software.com/2020/12/01/rockchip-rk3568-processor-to-power-edge-computing-and-nvr-applications 22nm process, believed to be FD-SOI]

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 4GB, 8GB LPDDR4.

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB
** Model A: 2 USB 2.0 host ports, 1 USB 2.0 OTG port, 1 USB 3.0 host port
** Model B: 1 USB 2.0 host port, 1 USB 2.0 OTG port, 1 USB 3.0 host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 16GB up to 128GB

==== eMMC Speeds ====

On a 64 GB eMMC module:

$ sudo hdparm -tT /dev/mmcblk1

/dev/mmcblk1:
Timing cached reads: 2368 MB in 2.00 seconds = 1184.46 MB/sec
Timing buffered disk reads: 452 MB in 3.01 seconds = 149.98 MB/sec

=== Expansion Ports ===
* HDMI
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints

The PCIe implementation on the RK3566 is much more compatible with a wide range of devices compared to the one on the RK3399 used on the ROCKPro64. This means a lot more devices should work (excluding dGPUs due to a lack of cache snooping ability). As an example, PCIe-to-PCI bridges work, whereas they didn't on the ROCKPro64.

==== Combo PHYs ====

[[File:rk3566 phy.png]]

Several of the I/O options on the RK3566 used in the Quartz64 are using the same I/O lines, meaning that they cannot be used at the same time. The above diagram illustrates how they are connected.

In particular, USB 3.0 and the SATA connector on the board are mutually exclusive, and the PCI-e 2.0 lane can be reconfigured into a second SATA port, though an adapter cable needs to be fashioned for this to be useful.

=== GPIO Pins (Quartz64 Model A) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX a
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX a
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT c
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

====Notes====
<ol style="list-style-type:lower-alpha">
<li>can be a PWM pin</li>
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
<li>low-pass filtered with cutoff of 220 MHz</li>
</ol>

Source: Page 28 of [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf the board schematics].

== Quartz64 Board Information, Schematics, and Certifications ==
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Quartz64 Model "A" SBC Schematic ver 2.0 20210427 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V2.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** Quartz64 Model "B" SBC Schematic not yet available
** [https://files.pine64.org/doc/quartz64/Quartz64%20model-B%20PCB%20placement.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]

* Certifications:
** Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary. However, PINE64 still submit the SBC for FCC and CE certification and obtain the certificates to proof that SBC board is capable on passing the testing. Please note a final commercial product needs to performs its owns testing and obtains its owns certificates.
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20CE%20certification-S21051101701001.pdf Quartz64 model-A FCC Certificate]
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20FCC%20certification-S21051101702001.pdf Quartz64 model-A CE Certificate]

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK817%20datasheet%20V1.01.pdf Rockchip RK817 ver 1.01 datasheet for Quartz64 model A]
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for Quartz64 model B and SOQuartz]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
** [https://files.pine64.org/doc/datasheet/PineNote/TI%20PMU-TPS651851.pdf TPS65185x PMIC for E-Ink Enabled Electronic Paper Display Datasheet]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

=== Android 11 Production Test Build for Quartz64 model A SBC ===

==== Android 11 Stock Image [eMMC Boot] using DD method [20210604] ====
* DD image to eMMC module using USB adapter for eMMC module and boot. Highly recommend using [https://etcher.io/ Etcher]
* This is test build that used during product testing
* Please allow 3-5 minutes boot up time on first time for initialization
* DD image for 8GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-8GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): e4365753e584d9fce1b8f10f095eede6
*** File Size: 819MB
* DD image for 16GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-16GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 491c5f7744b0ca0b74ae76e607051836
*** File Size: 1.10GB
* DD image for 32GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-32GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 47a6f0cdac8bad06cb920743849a8894
*** File Size: 846MB
* DD image for 64GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-64GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 4e2fed6f5db0d55afdc8a142fc0c4fe1
*** File Size: 884MB

==== Android 11 Production Test Build for Quartz64 model A SBC [eMMC Boot] using ROCKChip tools method [20210604] ====
* Please unzip first and then using [https://files.pine64.org/os/Quartz64//android/RKDevTool_Release_v2.84.zip Rockchip Android tool ver 2.84] to flash in
* For Windows OS environment, please install the [https://files.pine64.org/os/Quartz64/android/DriverAssitant_v5.1.1.zip DriverAssistant v5.11] driver first
* This is test build that used during product testing
* The OTG port located at top USB 2.0 port on top of USB 3.0 port, needs USB type A to type A cable.
* Please allow 3-5 minutes boot up time on first time for initialization
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_20210604_stock_android11_emmcboot.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 800f867fdd0d1b2bd7822c156b6067e3
*** File Size: 812MB

=== Android 11 eink SDK for Quartz64 model A SBC ===
* The is the Android SDK build for 10.3" eink panel on Quartz64 model A SBC.
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_eink.android11_SDK.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 293a550584298de4fb95ceae18103672
** File Size: 72.88GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Enclosures ==

All enclosures that fit the ROCKPro64 should fit the Quartz64, as the I/O has been laid out the same on purpose.

* [["Model A" Acrylic Open Enclosure]]
* [[ROCKPro64 ABS Enclosure]]

(Please expand this section with more cases known to work.)

== Troubleshooting ==

=== Stability/Boot Issues With Missing Battery Shunt ===

If there is no battery plugged into the board, the jumper labelled "ON/OFF_BATT" must be in place. If this is set wrong, stability issues such as failures to boot will occur.

=== No Ethernet Connectivity ===

Make sure the kernel is built with <code>CONFIG_MOTORCOMM_PHY</code> set to <code>y</code>. Building it as a module (<code>m</code>) and then relying on module auto-loading is unlikely to work as the PHY chip lacks its manufacturer ID.

=== "Model A" Acrylic Case Doesn't Fit ===

The Quartz64 does not really fit onto the bottom plate of the [["Model A" Acrylic Open Enclosure]]. This is because the "Mic" connector at the bottom of the board interferes with one of the posts. A workaround is to find out which post that is (you have a 50% chance of guessing it right, accounting for rotating the board) and then filing away the corner of the post pointing inwards by a few millimetres.

An alternate solution may be to place plastic spacers with a smaller outer diameter in between the acrylic bottom plate posts and the SBC board.

[[Category:Quartz64]]

Quartz64

2021-11-23T20:42:54Z

Bullet64: /* Manjaro ARM with desktop */

[[File:Quartz64modelb.png|400px|thumb|right|The Quartz64 Model B]]

The '''Quartz64''' is the most recent Single Board Computer offering from PINE64, initially released in June of 2021. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software releases ==

{{warning|Software for the Quartz64 is still early in development, and therefore currently lacks features such as the ability to produce video output. You are strongly encouraged to procure a 3.3V UART serial adapter capable of running at 1.5 mbauds, such as [https://pine64.com/product/serial-console-woodpecker-edition/ the woodpecker] if you want to use a Quartz64 at this stage.}}

=== Manjaro ARM ===
[[File:Manjaro.png|right|100px]]

Manjaro ARM is a user friendly rolling release distribution, based on Arch Linux ARM.

==== Manjaro ARM with no desktop ====

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images on Github]

==== Manjaro ARM with desktop ====

Since '''Dev 20211117''' with hdmi output (with linux-rc)

* Gnome
* KDE Plasma
* Mate
* Sway
* XFCE

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images on Github]

Note: Video out only working on 4 GB boards with 1080p monitors right now as the VOP2 patches are very early.

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support
* [https://www.cnx-software.com/2020/12/01/rockchip-rk3568-processor-to-power-edge-computing-and-nvr-applications 22nm process, believed to be FD-SOI]

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 4GB, 8GB LPDDR4.

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB
** Model A: 2 USB 2.0 host ports, 1 USB 2.0 OTG port, 1 USB 3.0 host port
** Model B: 1 USB 2.0 host port, 1 USB 2.0 OTG port, 1 USB 3.0 host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 16GB up to 128GB

==== eMMC Speeds ====

On a 64 GB eMMC module:

$ sudo hdparm -tT /dev/mmcblk1

/dev/mmcblk1:
Timing cached reads: 2368 MB in 2.00 seconds = 1184.46 MB/sec
Timing buffered disk reads: 452 MB in 3.01 seconds = 149.98 MB/sec

=== Expansion Ports ===
* HDMI
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints

The PCIe implementation on the RK3566 is much more compatible with a wide range of devices compared to the one on the RK3399 used on the ROCKPro64. This means a lot more devices should work (excluding dGPUs due to a lack of cache snooping ability). As an example, PCIe-to-PCI bridges work, whereas they didn't on the ROCKPro64.

==== Combo PHYs ====

[[File:rk3566 phy.png]]

Several of the I/O options on the RK3566 used in the Quartz64 are using the same I/O lines, meaning that they cannot be used at the same time. The above diagram illustrates how they are connected.

In particular, USB 3.0 and the SATA connector on the board are mutually exclusive, and the PCI-e 2.0 lane can be reconfigured into a second SATA port, though an adapter cable needs to be fashioned for this to be useful.

=== GPIO Pins (Quartz64 Model A) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX a
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX a
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT c
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

====Notes====
<ol style="list-style-type:lower-alpha">
<li>can be a PWM pin</li>
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
<li>low-pass filtered with cutoff of 220 MHz</li>
</ol>

Source: Page 28 of [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf the board schematics].

== Quartz64 Board Information, Schematics, and Certifications ==
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Quartz64 Model "A" SBC Schematic ver 2.0 20210427 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V2.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** Quartz64 Model "B" SBC Schematic not yet available
** [https://files.pine64.org/doc/quartz64/Quartz64%20model-B%20PCB%20placement.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]

* Certifications:
** Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary. However, PINE64 still submit the SBC for FCC and CE certification and obtain the certificates to proof that SBC board is capable on passing the testing. Please note a final commercial product needs to performs its owns testing and obtains its owns certificates.
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20CE%20certification-S21051101701001.pdf Quartz64 model-A FCC Certificate]
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20FCC%20certification-S21051101702001.pdf Quartz64 model-A CE Certificate]

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK817%20datasheet%20V1.01.pdf Rockchip RK817 ver 1.01 datasheet for Quartz64 model A]
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for Quartz64 model B and SOQuartz]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
** [https://files.pine64.org/doc/datasheet/PineNote/TI%20PMU-TPS651851.pdf TPS65185x PMIC for E-Ink Enabled Electronic Paper Display Datasheet]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

=== Android 11 Production Test Build for Quartz64 model A SBC ===

==== Android 11 Stock Image [eMMC Boot] using DD method [20210604] ====
* DD image to eMMC module using USB adapter for eMMC module and boot. Highly recommend using [https://etcher.io/ Etcher]
* This is test build that used during product testing
* Please allow 3-5 minutes boot up time on first time for initialization
* DD image for 8GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-8GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): e4365753e584d9fce1b8f10f095eede6
*** File Size: 819MB
* DD image for 16GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-16GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 491c5f7744b0ca0b74ae76e607051836
*** File Size: 1.10GB
* DD image for 32GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-32GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 47a6f0cdac8bad06cb920743849a8894
*** File Size: 846MB
* DD image for 64GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-64GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 4e2fed6f5db0d55afdc8a142fc0c4fe1
*** File Size: 884MB

==== Android 11 Production Test Build for Quartz64 model A SBC [eMMC Boot] using ROCKChip tools method [20210604] ====
* Please unzip first and then using [https://files.pine64.org/os/Quartz64//android/RKDevTool_Release_v2.84.zip Rockchip Android tool ver 2.84] to flash in
* For Windows OS environment, please install the [https://files.pine64.org/os/Quartz64/android/DriverAssitant_v5.1.1.zip DriverAssistant v5.11] driver first
* This is test build that used during product testing
* The OTG port located at top USB 2.0 port on top of USB 3.0 port, needs USB type A to type A cable.
* Please allow 3-5 minutes boot up time on first time for initialization
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_20210604_stock_android11_emmcboot.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 800f867fdd0d1b2bd7822c156b6067e3
*** File Size: 812MB

=== Android 11 eink SDK for Quartz64 model A SBC ===
* The is the Android SDK build for 10.3" eink panel on Quartz64 model A SBC.
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_eink.android11_SDK.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 293a550584298de4fb95ceae18103672
** File Size: 72.88GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Enclosures ==

All enclosures that fit the ROCKPro64 should fit the Quartz64, as the I/O has been laid out the same on purpose.

* [["Model A" Acrylic Open Enclosure]]
* [[ROCKPro64 ABS Enclosure]]

(Please expand this section with more cases known to work.)

== Troubleshooting ==

=== Stability/Boot Issues With Missing Battery Shunt ===

If there is no battery plugged into the board, the jumper labelled "ON/OFF_BATT" must be in place. If this is set wrong, stability issues such as failures to boot will occur.

=== No Ethernet Connectivity ===

Make sure the kernel is built with <code>CONFIG_MOTORCOMM_PHY</code> set to <code>y</code>. Building it as a module (<code>m</code>) and then relying on module auto-loading is unlikely to work as the PHY chip lacks its manufacturer ID.

=== "Model A" Acrylic Case Doesn't Fit ===

The Quartz64 does not really fit onto the bottom plate of the [["Model A" Acrylic Open Enclosure]]. This is because the "Mic" connector at the bottom of the board interferes with one of the posts. A workaround is to find out which post that is (you have a 50% chance of guessing it right, accounting for rotating the board) and then filing away the corner of the post pointing inwards by a few millimetres.

An alternate solution may be to place plastic spacers with a smaller outer diameter in between the acrylic bottom plate posts and the SBC board.

[[Category:Quartz64]]

Quartz64

2021-11-23T20:37:43Z

Bullet64: /* Manjaro ARM with desktop */

[[File:Quartz64modelb.png|400px|thumb|right|The Quartz64 Model B]]

The '''Quartz64''' is the most recent Single Board Computer offering from PINE64, initially released in June of 2021. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software releases ==

{{warning|Software for the Quartz64 is still early in development, and therefore currently lacks features such as the ability to produce video output. You are strongly encouraged to procure a 3.3V UART serial adapter capable of running at 1.5 mbauds, such as [https://pine64.com/product/serial-console-woodpecker-edition/ the woodpecker] if you want to use a Quartz64 at this stage.}}

=== Manjaro ARM ===
[[File:Manjaro.png|right|100px]]

Manjaro ARM is a user friendly rolling release distribution, based on Arch Linux ARM.

==== Manjaro ARM with no desktop ====

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images on Github]

==== Manjaro ARM with desktop ====

Since '''Dev 20211117''' with hdmi output (with linux-rc)

* Gnome
* KDE Plasma
* Mate
* Sway
* XFCE

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images on Github]

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support
* [https://www.cnx-software.com/2020/12/01/rockchip-rk3568-processor-to-power-edge-computing-and-nvr-applications 22nm process, believed to be FD-SOI]

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 4GB, 8GB LPDDR4.

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB
** Model A: 2 USB 2.0 host ports, 1 USB 2.0 OTG port, 1 USB 3.0 host port
** Model B: 1 USB 2.0 host port, 1 USB 2.0 OTG port, 1 USB 3.0 host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 16GB up to 128GB

==== eMMC Speeds ====

On a 64 GB eMMC module:

$ sudo hdparm -tT /dev/mmcblk1

/dev/mmcblk1:
Timing cached reads: 2368 MB in 2.00 seconds = 1184.46 MB/sec
Timing buffered disk reads: 452 MB in 3.01 seconds = 149.98 MB/sec

=== Expansion Ports ===
* HDMI
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints

The PCIe implementation on the RK3566 is much more compatible with a wide range of devices compared to the one on the RK3399 used on the ROCKPro64. This means a lot more devices should work (excluding dGPUs due to a lack of cache snooping ability). As an example, PCIe-to-PCI bridges work, whereas they didn't on the ROCKPro64.

==== Combo PHYs ====

[[File:rk3566 phy.png]]

Several of the I/O options on the RK3566 used in the Quartz64 are using the same I/O lines, meaning that they cannot be used at the same time. The above diagram illustrates how they are connected.

In particular, USB 3.0 and the SATA connector on the board are mutually exclusive, and the PCI-e 2.0 lane can be reconfigured into a second SATA port, though an adapter cable needs to be fashioned for this to be useful.

=== GPIO Pins (Quartz64 Model A) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX a
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX a
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT c
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

====Notes====
<ol style="list-style-type:lower-alpha">
<li>can be a PWM pin</li>
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
<li>low-pass filtered with cutoff of 220 MHz</li>
</ol>

Source: Page 28 of [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf the board schematics].

== Quartz64 Board Information, Schematics, and Certifications ==
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Quartz64 Model "A" SBC Schematic ver 2.0 20210427 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V2.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** Quartz64 Model "B" SBC Schematic not yet available
** [https://files.pine64.org/doc/quartz64/Quartz64%20model-B%20PCB%20placement.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]

* Certifications:
** Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary. However, PINE64 still submit the SBC for FCC and CE certification and obtain the certificates to proof that SBC board is capable on passing the testing. Please note a final commercial product needs to performs its owns testing and obtains its owns certificates.
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20CE%20certification-S21051101701001.pdf Quartz64 model-A FCC Certificate]
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20FCC%20certification-S21051101702001.pdf Quartz64 model-A CE Certificate]

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK817%20datasheet%20V1.01.pdf Rockchip RK817 ver 1.01 datasheet for Quartz64 model A]
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for Quartz64 model B and SOQuartz]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
** [https://files.pine64.org/doc/datasheet/PineNote/TI%20PMU-TPS651851.pdf TPS65185x PMIC for E-Ink Enabled Electronic Paper Display Datasheet]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

=== Android 11 Production Test Build for Quartz64 model A SBC ===

==== Android 11 Stock Image [eMMC Boot] using DD method [20210604] ====
* DD image to eMMC module using USB adapter for eMMC module and boot. Highly recommend using [https://etcher.io/ Etcher]
* This is test build that used during product testing
* Please allow 3-5 minutes boot up time on first time for initialization
* DD image for 8GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-8GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): e4365753e584d9fce1b8f10f095eede6
*** File Size: 819MB
* DD image for 16GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-16GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 491c5f7744b0ca0b74ae76e607051836
*** File Size: 1.10GB
* DD image for 32GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-32GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 47a6f0cdac8bad06cb920743849a8894
*** File Size: 846MB
* DD image for 64GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-64GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 4e2fed6f5db0d55afdc8a142fc0c4fe1
*** File Size: 884MB

==== Android 11 Production Test Build for Quartz64 model A SBC [eMMC Boot] using ROCKChip tools method [20210604] ====
* Please unzip first and then using [https://files.pine64.org/os/Quartz64//android/RKDevTool_Release_v2.84.zip Rockchip Android tool ver 2.84] to flash in
* For Windows OS environment, please install the [https://files.pine64.org/os/Quartz64/android/DriverAssitant_v5.1.1.zip DriverAssistant v5.11] driver first
* This is test build that used during product testing
* The OTG port located at top USB 2.0 port on top of USB 3.0 port, needs USB type A to type A cable.
* Please allow 3-5 minutes boot up time on first time for initialization
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_20210604_stock_android11_emmcboot.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 800f867fdd0d1b2bd7822c156b6067e3
*** File Size: 812MB

=== Android 11 eink SDK for Quartz64 model A SBC ===
* The is the Android SDK build for 10.3" eink panel on Quartz64 model A SBC.
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_eink.android11_SDK.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 293a550584298de4fb95ceae18103672
** File Size: 72.88GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Enclosures ==

All enclosures that fit the ROCKPro64 should fit the Quartz64, as the I/O has been laid out the same on purpose.

* [["Model A" Acrylic Open Enclosure]]
* [[ROCKPro64 ABS Enclosure]]

(Please expand this section with more cases known to work.)

== Troubleshooting ==

=== Stability/Boot Issues With Missing Battery Shunt ===

If there is no battery plugged into the board, the jumper labelled "ON/OFF_BATT" must be in place. If this is set wrong, stability issues such as failures to boot will occur.

=== No Ethernet Connectivity ===

Make sure the kernel is built with <code>CONFIG_MOTORCOMM_PHY</code> set to <code>y</code>. Building it as a module (<code>m</code>) and then relying on module auto-loading is unlikely to work as the PHY chip lacks its manufacturer ID.

=== "Model A" Acrylic Case Doesn't Fit ===

The Quartz64 does not really fit onto the bottom plate of the [["Model A" Acrylic Open Enclosure]]. This is because the "Mic" connector at the bottom of the board interferes with one of the posts. A workaround is to find out which post that is (you have a 50% chance of guessing it right, accounting for rotating the board) and then filing away the corner of the post pointing inwards by a few millimetres.

An alternate solution may be to place plastic spacers with a smaller outer diameter in between the acrylic bottom plate posts and the SBC board.

[[Category:Quartz64]]

Quartz64

2021-11-23T20:36:01Z

Bullet64: /* Manjaro ARM with no desktop */

[[File:Quartz64modelb.png|400px|thumb|right|The Quartz64 Model B]]

The '''Quartz64''' is the most recent Single Board Computer offering from PINE64, initially released in June of 2021. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is an eMMC module socket (supporting up to 128GB) and microSD slot, as well as a footprint to solder on an SPI flash chip. The board is equipped with HDMI, 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software releases ==

{{warning|Software for the Quartz64 is still early in development, and therefore currently lacks features such as the ability to produce video output. You are strongly encouraged to procure a 3.3V UART serial adapter capable of running at 1.5 mbauds, such as [https://pine64.com/product/serial-console-woodpecker-edition/ the woodpecker] if you want to use a Quartz64 at this stage.}}

=== Manjaro ARM ===
[[File:Manjaro.png|right|100px]]

Manjaro ARM is a user friendly rolling release distribution, based on Arch Linux ARM.

==== Manjaro ARM with no desktop ====

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images on Github]

==== Manjaro ARM with desktop ====

Since Dev 20211117 with hdmi output (with linux-rc)

* Gnome
* KDE Plasma
* Mate
* Sway
* XFCE

* [https://github.com/manjaro-arm/quartz64-bsp-images/releases Weekly images on Github]

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support
* [https://www.cnx-software.com/2020/12/01/rockchip-rk3568-processor-to-power-edge-computing-and-nvr-applications 22nm process, believed to be FD-SOI]

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 4GB, 8GB LPDDR4.

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB
** Model A: 2 USB 2.0 host ports, 1 USB 2.0 OTG port, 1 USB 3.0 host port
** Model B: 1 USB 2.0 host port, 1 USB 2.0 OTG port, 1 USB 3.0 host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 16GB up to 128GB

==== eMMC Speeds ====

On a 64 GB eMMC module:

$ sudo hdparm -tT /dev/mmcblk1

/dev/mmcblk1:
Timing cached reads: 2368 MB in 2.00 seconds = 1184.46 MB/sec
Timing buffered disk reads: 452 MB in 3.01 seconds = 149.98 MB/sec

=== Expansion Ports ===
* HDMI
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints

The PCIe implementation on the RK3566 is much more compatible with a wide range of devices compared to the one on the RK3399 used on the ROCKPro64. This means a lot more devices should work (excluding dGPUs due to a lack of cache snooping ability). As an example, PCIe-to-PCI bridges work, whereas they didn't on the ROCKPro64.

==== Combo PHYs ====

[[File:rk3566 phy.png]]

Several of the I/O options on the RK3566 used in the Quartz64 are using the same I/O lines, meaning that they cannot be used at the same time. The above diagram illustrates how they are connected.

In particular, USB 3.0 and the SATA connector on the board are mutually exclusive, and the PCI-e 2.0 lane can be reconfigured into a second SATA port, though an adapter cable needs to be fashioned for this to be useful.

=== GPIO Pins (Quartz64 Model A) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0 a,b
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX a
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX a
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT c
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

====Notes====
<ol style="list-style-type:lower-alpha">
<li>can be a PWM pin</li>
<li>pulled high to 3.3V through 2.2kOhm resistor</li>
<li>low-pass filtered with cutoff of 220 MHz</li>
</ol>

Source: Page 28 of [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf the board schematics].

== Quartz64 Board Information, Schematics, and Certifications ==
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Quartz64 Model "A" SBC Schematic ver 2.0 20210427 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V2.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** Quartz64 Model "B" SBC Schematic not yet available
** [https://files.pine64.org/doc/quartz64/Quartz64%20model-B%20PCB%20placement.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]

* Certifications:
** Disclaimer: Please note that PINE64 SBC is not a "final" product and in general certification is not necessary. However, PINE64 still submit the SBC for FCC and CE certification and obtain the certificates to proof that SBC board is capable on passing the testing. Please note a final commercial product needs to performs its owns testing and obtains its owns certificates.
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20CE%20certification-S21051101701001.pdf Quartz64 model-A FCC Certificate]
** [https://files.pine64.org/doc/cert/Quartz64%20Model-A%20FCC%20certification-S21051101702001.pdf Quartz64 model-A CE Certificate]

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* Rockchip PMU (Power Management Unit) Information:
** [https://www.rockchip.fr/RK817%20datasheet%20V1.01.pdf Rockchip RK817 ver 1.01 datasheet for Quartz64 model A]
** [https://www.rockchip.fr/RK809%20datasheet%20V1.01.pdf Rockchip RK809 ver 1.01 datasheet for Quartz64 model B and SOQuartz]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
** [https://files.pine64.org/doc/datasheet/PineNote/TI%20PMU-TPS651851.pdf TPS65185x PMIC for E-Ink Enabled Electronic Paper Display Datasheet]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AW-CM256SM_DS_DF_V1.9_STD.pdf Azurewave CM256SM 11AC WiFi + Bluetooth5.0 Datasheet]]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== BSP Linux SDK ==

=== BSP Linux SDK ver 4.19 for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_BSP%20Linux.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 24554419aec29700add97167a3a4c9ed
** File Size: 32.67.00GB

== Android SDK ==

=== Android 11 SDK for Quartz64 model A SBC ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

=== Android 11 Production Test Build for Quartz64 model A SBC ===

==== Android 11 Stock Image [eMMC Boot] using DD method [20210604] ====
* DD image to eMMC module using USB adapter for eMMC module and boot. Highly recommend using [https://etcher.io/ Etcher]
* This is test build that used during product testing
* Please allow 3-5 minutes boot up time on first time for initialization
* DD image for 8GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-8GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): e4365753e584d9fce1b8f10f095eede6
*** File Size: 819MB
* DD image for 16GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-16GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 491c5f7744b0ca0b74ae76e607051836
*** File Size: 1.10GB
* DD image for 32GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-32GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 47a6f0cdac8bad06cb920743849a8894
*** File Size: 846MB
* DD image for 64GB eMMC module
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_dd_20210604_stock_android11_emmcboot-64GB.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 4e2fed6f5db0d55afdc8a142fc0c4fe1
*** File Size: 884MB

==== Android 11 Production Test Build for Quartz64 model A SBC [eMMC Boot] using ROCKChip tools method [20210604] ====
* Please unzip first and then using [https://files.pine64.org/os/Quartz64//android/RKDevTool_Release_v2.84.zip Rockchip Android tool ver 2.84] to flash in
* For Windows OS environment, please install the [https://files.pine64.org/os/Quartz64/android/DriverAssitant_v5.1.1.zip DriverAssistant v5.11] driver first
* This is test build that used during product testing
* The OTG port located at top USB 2.0 port on top of USB 3.0 port, needs USB type A to type A cable.
* Please allow 3-5 minutes boot up time on first time for initialization
** [https://files.pine64.org/os/Quartz64/android/Quartz64_model-A_20210604_stock_android11_emmcboot.img.gz Direct download from pine64.org]
*** MD5 (GZip file): 800f867fdd0d1b2bd7822c156b6067e3
*** File Size: 812MB

=== Android 11 eink SDK for Quartz64 model A SBC ===
* The is the Android SDK build for 10.3" eink panel on Quartz64 model A SBC.
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64-model-A_eink.android11_SDK.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 293a550584298de4fb95ceae18103672
** File Size: 72.88GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Enclosures ==

All enclosures that fit the ROCKPro64 should fit the Quartz64, as the I/O has been laid out the same on purpose.

* [["Model A" Acrylic Open Enclosure]]
* [[ROCKPro64 ABS Enclosure]]

(Please expand this section with more cases known to work.)

== Troubleshooting ==

=== Stability/Boot Issues With Missing Battery Shunt ===

If there is no battery plugged into the board, the jumper labelled "ON/OFF_BATT" must be in place. If this is set wrong, stability issues such as failures to boot will occur.

=== No Ethernet Connectivity ===

Make sure the kernel is built with <code>CONFIG_MOTORCOMM_PHY</code> set to <code>y</code>. Building it as a module (<code>m</code>) and then relying on module auto-loading is unlikely to work as the PHY chip lacks its manufacturer ID.

=== "Model A" Acrylic Case Doesn't Fit ===

The Quartz64 does not really fit onto the bottom plate of the [["Model A" Acrylic Open Enclosure]]. This is because the "Mic" connector at the bottom of the board interferes with one of the posts. A workaround is to find out which post that is (you have a 50% chance of guessing it right, accounting for rotating the board) and then filing away the corner of the post pointing inwards by a few millimetres.

An alternate solution may be to place plastic spacers with a smaller outer diameter in between the acrylic bottom plate posts and the SBC board.

[[Category:Quartz64]]

Quartz64

2021-06-27T16:00:52Z

Bullet64: /* GPIO Pins */

The Quartz64 is the most recent Single Board Computer offering from Pine64, scheduled for release in 2021. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is a 128Mb SPI boot Flash, an eMMC module socket (supporting up to 128GB) and microSD slot. The board is equipped with 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software and OS Image Downloads ==

* TBD

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB, 4GB, 8GB LPDDR4.
* SPI Flash: 128Mbit / 16MByte

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB - 2 ports on model B, 3 ports on model A USB 2.0 Host port, 1 USB 3.0 Host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 16GB up to 128GB

=== Expansion Ports ===
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints

=== GPIO Pins ( Quartz64 Model A) ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

Source: Page28 https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf

== Quartz64 Board Information, Schematics, and Certifications ==
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf Quartz64 Model "A" SBC Schematic ver 1.0 20201215 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v1.0_20201124.pdf Quartz64 Model "A" SBC Schematic ver 1.0 20201124 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V1.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** Quartz64 Model "B" SBC Schematic not yet available
** [https://files.pine64.org/doc/quartz64/Quartz64%20model-B%20PCB%20placement.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]

* Certification:
** Not yet available

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AP6256%20datasheet_V1.3_12202017.pdf AMPAK AP6256 11AC WiFi + Bluetooth5.0 Datasheet]]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== Android SDK ==

=== Android 11 SDK ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Other Resources ==

[[Category:Quartz64]]

Quartz64

2021-06-26T06:45:35Z

Bullet64: /* Expansion Ports */

The Quartz64 is the most recent Single Board Computer offering from Pine64, scheduled for release in 2021. It is powered by a Rockchip RK3566 Quad-Core ARM Cortex A55 64-Bit Processor with a MALI G-52 GPU.

Key features include a PCIe x4 open ended slot (model A) or m.2 (model B) using one Gen2 lane electrically, and the use of LPDDR4 RAM.

The Quartz64 has three LPDDR4 system memory options: 2GB, 4GB or 8GB. For booting, there is a 128Mb SPI boot Flash, an eMMC module socket (supporting up to 128GB) and microSD slot. The board is equipped with 1x USB 3.0 type A Host, 3x USB 2.0 Host, Gigabit Ethernet, SATA (model A), GPIO Bus, MiPi DSI interface, e-ink interface (model A), eDP interface (model A), touch Panel interface (model A), MiPi CSI interface, as well as many other device interfaces such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Many different Operating Systems (OS) are freely available from the open source community, such as Linux (Ubuntu, Debian, Arch), BSD, and Android.

== Software and OS Image Downloads ==

* TBD

== SoC and Memory Specifications ==
* Based on [https://www.rock-chips.com/a/en/products/RK35_Series/2021/0113/1274.html Rockchip RK3566]
[[File:RK3566_icon.png|right]]

=== CPU Architecture ===
* [https://developer.arm.com/ip-products/processors/cortex-a/cortex-a55 Quad-core ARM Cortex-A55@1.8GHz]
* AArch32 for full backwards compatibility with ARMv7
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* Includes VFP hardware to support single and double-precision operations
* ARMv8 Cryptography Extensions
* Integrated 32KB L1 instruction cache and 32KB L1 data cache per core
* 512KB unified system L3 cache
* [https://developer.arm.com/ip-products/security-ip/trustzone TrustZone] technology support

=== GPU (Graphics Processing Unit) Capabilities ===
* [https://developer.arm.com/ip-products/graphics-and-multimedia/mali-gpus/mali-g52-gpu Mali-G52 2EE Bifrost GPU@800MHz]
* 4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop
* 128KB L2 Cache configurations
* Supports OpenGL ES 1.1, 2.0, and 3.2
* Supports Vulkan 1.0 and 1.1
* Supports OpenCL 2.0 Full Profile
* Supports 1600 Mpix/s fill rate when at 800MHz clock frequency
* Supports 38.4 GLOP/s when at 800MHz clock frequency

=== NPU (Neural Processing Unit) Capabilities ===
* Neural network acceleration engine with processing performance of up to 0.8 TOPS
* Supports integer 8 and integer 16 convolution operations
* Supports the following deep learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet, Keras, Darknet

=== System Memory ===
* RAM Memory Variants: 2GB, 4GB, 8GB LPDDR4.
* SPI Flash: 128Mbit / 16MByte

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 b/g/n/ac with Bluetooth 5.0 (optional on model A, built in on model B)

=== Storage ===
* microSD - bootable, supports SDHC and SDXC, storage up to 2TB
* USB - 2 ports on model B, 3 ports on model A USB 2.0 Host port, 1 USB 3.0 Host port
* one native SATA 3.0 6Gb/s Port (only on model A, shared with USB 3.0 host port)
* optional eMMC module from 16GB up to 128GB

=== Expansion Ports ===
* eDP - 4 lanes of 2.7Gbps, up to 2560x1600@60Hz (only on model A)
* DSI - Display Serial Interface, 4 lanes MiPi, up to 1440P on model A, 2 lanes MiPi, up to 1080p on model B
* CSI - CMOS Camera Interface, 4 lanes MiPi up to 8 mega pixel on model A, 2 lanes MiPi up to 5 mega pixel on model B
* TP - Touch Panel Port, SPI with interrupt on model A
* RTC - Real Time Clock Battery Connector
* VBAT - Lithium Battery Connector with temperature sensor input on model A
* Wifi/BT Module Header - SDIO 3.0 and UART on model A, build in Wifi/BT Module on model B
* 2x20 pins "Pi2" GPIO Header on model B, 2x10 pins GPO header on model A
* PCIe x4 open ended slot on model A, m.2 slot on model B, one Gen2 lane due to SoC constraints

=== GPIO Pins ===

Attention! GPIOs are 3.3V!

{| class="wikitable plainrowheaders" border="1"
! scope="col" style="width:20em;" | Assigned To
! scope="col" | Pin Nr.
! scope="col" | Pin Nr.
! scope="col" style="width:20em;" | Assigned To
|-
| style="text-align:right;"| 3.3 V
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 2
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SDA_M0
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 3
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 4
| style="text-align:left;"| 5 V
|-
| style="text-align:right;"| I2C3_SCL_M0
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 5
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 6
| style="text-align:left;"| GND
|-
| style="text-align:right;"| CPU_REFCLK_OUT
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 7
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 8
| style="text-align:left;"| UART2_TX_M0_DEBUG
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 9
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 10
| style="text-align:left;"| UART2_RX_M0_DEBUG
|-
| style="text-align:right;"| SPI1_MOSI_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 11
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 12
| style="text-align:left;"| UART0_TX
|-
| style="text-align:right;"| SPI1_MISO_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 13
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 14
| style="text-align:left;"| UART0_RX
|-
| style="text-align:right;"| SPI1_CLK_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 15
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 16
| style="text-align:left;"| GND
|-
| style="text-align:right;"| SPI1_CS0_M1
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 17
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 18
| style="text-align:left;"| SPDIF_OUT
|-
| style="text-align:right;"| GND
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 19
| style="text-align:center; background-color:black; color:gold; font-weight:bold;"| 20
| style="text-align:left;"| 3.3V
|}

Source: Page28 https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf

== Quartz64 Board Information, Schematics, and Certifications ==
* Model "A" Baseboard Dimensions: 133mm x 80mm x 19mm
* Input Power: DC 12V @ 3A 5.5mmOD/2.1mmID center-positive Barrel DC Jack connector

* Quartz64 Model "A" SBC Schematic and PCB Board Resource:
** [https://wiki.pine64.org/images/3/31/Quartz64_model-A_schematic_v1.0_20201215.pdf Quartz64 Model "A" SBC Schematic ver 1.0 20201215 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v1.0_20201124.pdf Quartz64 Model "A" SBC Schematic ver 1.0 20201124 PDF file]
** [https://files.pine64.org/doc/quartz64/Quartz64_model-A_V1.0_connector_placement.pdf Quartz64 Model "A" SBC PCB Connector placement PDF file]

* Model "B" Baseboard Dimensions: 85mm x 56mm x 18.8mm
* Input Power: DC 5V @ 3A 3.5mmOD/1.35mmID Barrel DC Jack connector

* Quartz64 Model "B" SBC Schematic and PCB Board Resource:
** Quartz64 Model "B" SBC Schematic not yet available
** [https://files.pine64.org/doc/quartz64/Quartz64%20model-B%20PCB%20placement.pdf Quartz64 Model "B" SBC PCB Connector placement PDF file]

* Certification:
** Not yet available

== Datasheets for Components and Peripherals ==
* Rockchip RK3566 SoC information:
** [https://files.pine64.org/doc/quartz64/Rockchip%20RK3566%20Datasheet%20V1.0-20201210.pdf Rockchip RK3566 ver 1.0 datasheet, already got release permission from Rockchip]
* LPDDR4 (200 Balls) SDRAM:
** [https://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [https://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [https://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [https://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [https://files.pine64.org/doc/datasheet/pine64/E-00517%20FORESEE_eMMC_NCEMAM8B-16G%20SPEC.pdf 16GB Foresee eMMC Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf 32GB/64GB/128GB SanDisk eMMC Datasheet]
* SPI NOR Flash information:
** [https://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [https://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* E-ink Panel information:
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-754-V3_ES103TC1%20Specification%20V3.0(Signed)-20190702.pdf Eink 10.3" 1872x1404 ES103TC1 Flex Panel Specification]
** [https://files.pine64.org/doc/quartz64/Eink%20P-511-828-V1_ED103TC2%20Formal%20Spec%20V1.0_20190514.pdf Eink 10.3" 1872x1404 ES103TC1 Glass Panel Specification]
* LCD Touch Screen Panel information:
** [https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf 7.0" 1200x600 TFT-LCD Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/HK70DR2459-PG-V01.pdf Touch Panel Specification]
** [https://files.pine64.org/doc/datasheet/pine64/GT911%20Capacitive%20Touch%20Controller%20Datasheet.pdf GOODiX GT911 5-Point Capacitive Touch Controller Datasheet]
* Ethernet PHY information:
** [https://files.pine64.org/doc/datasheet/pine64/rtl8211e(g)-vb(vl)-cg_datasheet_1.6.pdf Realtek RTL8211 10/100/1000M Ethernet Transceiver]
* WiFi/BT module info:
** [https://files.pine64.org/doc/datasheet/rockpro64/AP6256%20datasheet_V1.3_12202017.pdf AMPAK AP6256 11AC WiFi + Bluetooth5.0 Datasheet]]
* Enclosure information:
** [https://files.pine64.org/doc/datasheet/case/playbox_enclosure_20160426.stp Playbox Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/ABS_enclosure_20160426.stp ABS Enclosure 3D file]
** [https://files.pine64.org/doc/datasheet/case/pine64%20Die%20Cast%20casing-final.jpg Outdoor Aluminum Cast Dust-proof IP67 Enclosure Drawing]
* Connector information:
** [https://files.pine64.org/doc/datasheet/pine64/ePH.pdf 2.0mm PH Type connector specification use in Lithium Battery (VBAT) port and RTC Battery port]
** [https://files.pine64.org/doc/datasheet/pine64/0.5FPC%20Front%20Open%20Connector%20H=1.5.pdf 0.5mm Pitch cover type FPC connector specification use in DSI port, TP port and CSI port]

== Development efforts ==

{{SeeMainArticle|Quartz64 Development}}

Information and resources of the ongoing development effort for the Quartz64 can be found on the [[Quartz64 Development]] page, where the current status of various board functions can be found, and whether they have landed in upstream.

* [https://gitlab.com/pine64-org/quartz-bsp Quartz64 BSP Gitlab Page]

== Android SDK ==

=== Android 11 SDK ===
* [http://files.pine64.org/SDK/Quartz64/QUARTZ64_SDK_android11.tar.gz Direct Download from pine64.org]
** MD5 (TAR-GZip file): 77c2ff57ea3372fb04da7fb49e17d12b
** File Size: 79.00GB
** Just the boot blobs (<1MB): [[File:Rk35-blobs.tar.gz]]

== Other Resources ==

[[Category:Quartz64]]

ROCKPro64

2018-05-10T19:58:48Z

Bullet64:

== [https://www.pine64.org/rock64 ROCKPro64] ==
[https://www.pine64.org/rock64 ROCKPro64] ROCKPro64 is the most powerful Single Board Computer released by Pine64. Its powered by a Rockchip RK3399 Hexa-Core (dual ARM Cortex A72 and quad ARM Cortex A53) 64-Bit Processor with MALI T-860 Quad-Core GPU. The ROCKPro64 is equipped with 4GB LPDDR4 system memory and 128Mb SPI boot Flash. There is also an optional eMMC module (up to 128GB) and microSD slot for booting. The board is equipped with a PCIe x4 open ended slot, 1x USB 3.0 type C Host with DP 1.2, 1x USB 3.0 type A Host, 2x USB 2.0 Host, Gigabit Ethernet, PI-2 GPIO Bus, MiPi DSI interface, eDP interface, touch Panel interface, stereo MiPi CSI interface, as well as many other peripheral device interface such as UART, SPI, I2C, for makers to integrate with sensors and other peripherals. Various Operating System (OS) are made available by open source community such Android 7.1, Debian, Arch Linux and many more to come.

[[File:ROCKPro64_sideimg.jpg]]

== ROCKPro64 Software Images ==

* OS build Installation Guide and tools:
** [http://files.pine64.org/doc/rock64/guide/ROCK64_Installing_Android_To_eMMC.pdf Guide to install stock Android build to eMMC module]
** [http://files.pine64.org/doc/rock64/tools/SD_Firmware_Tool._v1.46.zip Tools to burn Android build into a bootable microSD card]
** [http://files.pine64.org/doc/rock64/tools/AndroidTool_Release_v2.38.zip Tools that allows developer flash image into eMMC's Loader/Parameter/Misc/Kernal/Boot/Recovery/System/Backup partition]
** [http://files.pine64.org/doc/rock64/tools/DriverAssitant_v4.5.zip Windows ADB driver package]
** [[Set MacAddress on ROCK64]]

----

=== [[ROCKPro64_Software_Release|ROCKPro64]] ===

Under [[ROCKPro64_Software_Release|'ROCKPro64 Software and OS Image Download Section']] you will find a complete list of currently supported Operating System images that work with the ROCKPro64 as well as other related software.
The list includes OS images and descriptions of:

== SoC and Memory Specification ==
* Based on Rockchip RK3399
[[File:Rockchip_RK3399.png]]

=== CPU Architecture ===
* [https://developer.arm.com/products/processors/cortex-a/cortex-a72 Dual-core Cortex-A72 up to 2.0GHz CPU]
* [https://developer.arm.com/products/processors/cortex-a/cortex-a53 Quad-core Cortex-A53 up to 1.5GHz CPU]
* Big.Little architecture: Dual Cortex-A72 + Quad Cortex-A53, 64-bit CPU
* Cortex-A72:
** 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 5 CHI or AMBA 4 ACE technology
** AArch64 for 64-bit support and new architectural features
** L1 cache 48KB Icache and 32KB Dcache for each A72
** L2 cache 1024KB for big cluster
** TrustZone security technology
** NEON advanced SIMD
** DSP & SIMD extensions
** VFPv4 floating point
** Hardware virtualization support
* Cortex A53:
** L1 cache 32KB Icache and 32KB Dcache for each A53
** L2 cache 512KB for little cluster
* Full implementation of the ARM architecture v8-A instruction set
* ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
* ARMv8 Cryptography Extensions
* In-order pipeline with symmetric dual-issue of most instructions
* Include VFP v3 hardware to support single and double-precision operations
* TrustZone technology support
* Full CoreSight debug solution
* One isolated voltage domain to support DVFS

=== GPU Architecture ===
* [https://developer.arm.com/products/graphics-and-multimedia/mali-gpus/mali-t860-and-mali-t880-gpus ARM Mali-T860MP4 Quad-core GPU]
* The highest performance GPUs built on Arm Mali’s famous Midgard architecture, the Mali-T860 GPU is designed for complex graphics use cases and provide stunning visuals for UHD content.
* Frequency 650MHz
* Throughput 1300Mtri/s, 10.4Gpix/s
* OpenGL® ES 1.1, 1.2, 2.0, 3.1, 3.2., Vulkan 1.0*., OpenCL™ 1.1, 1.2., DirectX® 11 FL11_1., RenderScript™.

=== System Memory ===
* LPDDR4 RAM Memory Variants: Dual Channels 2GB and 4GB.
* Storage Memory: ROCK64 boards have 128Mb built-in SPI Flash memory but not yet in use, currently use '''bootable microSD Cards''' or '''bootable attachable eMMC'''.

== Board Features ==

=== Display ===
* Dual VOP: one supports 4096x2160 with AFBC supported；The other supports 2560x1600
* Dual channel MIPI-DSI (4 lanes per channel)
* eDP 1.3 (4 lanes with 10.8Gbps) to support display, with PSR
* HDMI 2.0 for 4K 60Hz with HDCP 1.4/2.2
* DisplayPort 1.2 (4 lanes, up to 4K 60Hz)
* Supports Rec.2020 and conversion to Rec.709

=== Video ===
* HDMI 2.0a output up to 4K@60Hz
* 4K HDR @ 30fps
* H.264/AVC Base/Main/High/High10 profile @ level 5.1; up to 4Kx2K @ 60fps
* H.265/HEVC Main/Main10 profile @ level 5.1 High-tier; up to 4Kx2K @ 60fps
* VP9, up to 4Kx2K @ 60fps
* MPEG-1, ISO/IEC 11172-2, up to 1080P @ 60fps
* MPEG-2, ISO/IEC 13818-2, SP@ML, MP@HL, up to 1080P @ 60fps
* MPEG-4, ISO/IEC 14496-2, SP@L0-3, ASP@L0-5, up to 1080P @ 60fps
* VC-1, SP@ML, MP@HL, AP@L0-3, up to 1080P @ 60fps
* MVC is supported based on H.264 or H.265, up to 1080P @ 60fps

=== Audio ===
* 3.5mm Phone Jack

=== Camera ===
* Dual mipi CSI，dual ISP,Maximum input resolution of 13M pixels
*

=== Network ===
* 10/100/1000Mbps Ethernet
* WiFi 802.11 ac/a/b/g/n with Bluetooth 4.01 (optional)

=== Storage ===
* microSD - bootable, support SDHC and SDXC, storage up to 256GB
* eMMC - bootable (optional eMMC Module)
* 1 USB3.0 Host port
* 1 USB type C OTG port with DP output
* 2 USB2.0 Dedicated Host port (top one is USB-OTG)

=== Expansion Ports ===
* 2x20 pins "Pi2" GPIO Header
* PCIe 2.1 (4 full-duplex lanes with 20Gbps) x4 open ended port

== ROCKPro64 Board Information, Schematics and Certifications ==
* Board Dimensions: 133mm x 80mm x 19mm
* Input Power: +12V @3A/5A with 5.5mm/2.1mm Type M Barrel type DC connector
* [http://files.pine64.org/doc/rockpro64/RockPro64_Boardoutline%20Model.pdf ROCKPro64 Board Outline]
* [http://files.pine64.org/doc/rockpro64/rockpro64_v20-SCH.pdf ROCKPro64 Schematic v2.0 (Pilot Production Release)]
* [http://files.pine64.org/doc/rockpro64/Rockpro64%20Pi-2%20Connector%20ver0.2.png ROCK64 Pi-2 Pine assignment and defination]

* ROCK64 Certifications:
** FCC, CE, and RoHS Certification in progress

== Datasheets for Components and Peripherals ==
* Rockchip RK3399 SoC information:
** [http://www.rock-chips.com/a/en/products/RK33_Series/2016/0419/758.html Rockchip RK3399 SoC Brief]
** [http://opensource.rock-chips.com/images/6/60/Rockchip_RK3399_Datasheet_V1.6-20170301.pdf Rockchip RK3399 Datasheet V1.6]
** [http://opensource.rock-chips.com/images/e/ee/Rockchip_RK3399TRM_V1.4_Part1-20170408.pdf Rockchip RK3399 Technical Reference Manual part 1]
** [http://files.pine64.org/doc/datasheet/rockpro64/RK808%20datasheet%20V0.8.pdf Rockchip RK808 Datasheet V0.8]
* LPDDR4 (200 Balls) SDRAM:
** [http://files.pine64.org/doc/datasheet/rockpro64/SM512M32Z01MD2BNP(200BALL).pdf Micron LPDDR4 Mobile LPDDR4 Datasheet]
* eMMC information:
** [http://files.pine64.org/doc/rock64/PINE64_eMMC_Module_20170719.pdf PINE64 eMMC module schematic]
** [http://files.pine64.org/doc/rock64/usb%20emmc%20module%20adapter%20v2.pdf PINE64 USB adapter for eMMC module V2 schematic]
** [http://files.pine64.org/doc/rock64/USB%20adapter%20for%20eMMC%20module%20PCB.tar PINE64 USB adapter for eMMC module PCB in JPEG]
** [http://files.pine64.org/doc/datasheet/pine64/SDINADF4-16-128GB-H%20data%20sheet%20v1.13.pdf SanDisk eMMC Datasheet]
** [http://files.pine64.org/doc/datasheet/pine64/H26M64003DQR%20Datasheet.pdf Hynix eMMC Datasheet]
** [http://files.pine64.org/doc/datasheet/pine64/FORESEE_eMMC_NCEMBSF9-xxG%20SPEC%20A0%2020150730.pdf Foresee eMMC Datasheet]
* SPI NOR Flash information:
** [http://files.pine64.org/doc/datasheet/pine64/w25q128jv%20spi%20revc%2011162016.pdf WinBond 128Mb SPI Flash Datasheet]
** [http://files.pine64.org/doc/datasheet/pine64/GD25Q128C-Rev2.5.pdf GigaDevice 128Mb SPI Flash Datasheet]
* Heatsink related info:
** [http://files.pine64.org/doc/datasheet/rockpro64/Rockpro%20Passive%20Heatsink%20Spec.jpg ROCKPro64 Passive Heatsink Dimension Drawing]
** [http://files.pine64.org/doc/datasheet/rockpro64/LMS-TC150%20Silicon%20Thermal%20Pad.pdf Heatsink Thermal Pad Specification]
* Ethernet related info:
** [http://files.pine64.org/doc/datasheet/rock64/RTL8211F-CG-Realtek.pdf Realtek RTL8211F 10/100/1000M Ethernet Transceiver Datasheet]
* Peripheral related info:
** [http://files.pine64.org/doc/datasheet/rockpro64/ASM1061_Data%20Sheet_R1_8.pdf asmedia ASM1061 PCIe SATA 2.0 Datasheet]
* Remote control button mapping
** [http://files.pine64.org/doc/Pine%20A64%20Schematic/remote-wit-logo.jpg Official Remote Control for the PINE64 Button Mapping]

== Other Resources ==
* [https://forum.pine64.org/forumdisplay.php?fid=98 ROCKPro64 Forum]
* [http://www.pine64.xyz:9090/?channels=ROCK64 ROCK64/ROCKPro64 IRC Channel]
* [https://github.com/rockchip-linux Rockchip Linux GitHub Repo]
* [http://opensource.rock-chips.com/ Rockchip Open Source Wiki]
* [http://wiki.pine64.org/index.php/RockPro64_Guides ROCK64 Guides]